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dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra 1. general description the nxp lpc3152/3154 combine an 180 mhz arm926ej-s cpu core, high-speed usb 2.0 otg, 192 kb sram, nand flash controlle r, flexible external bus interface, an integrated audio codec, li-ion charger, real-t ime clock (rtc), and a myriad of serial and parallel interfaces in a single chip target ed at consumer, industrial, medical, and communication markets. to optimize syst em power consumptio n, the lpc3152/3154 have multiple power domains and a very fl exible clock generation unit (cgu) that provides dynamic clock gating and scaling. the lpc3152/3154 are implemented as a multi-chip module with two side-by-side dies, one for digital functions and one for analog functions, which include power supply unit (psu), audio codec, rtc, and li-ion battery charger. 2. features and benefits 2.1 key features ? cpu platform ? 180 mhz, 32-bit arm926ej-s ? 16 kb d-cache and 16 kb i-cache ? memory management unit (mmu) ? internal memory ? 192 kb embedded sram ? external memory interface ? nand flash controller with 8-bit ecc and aes decryption engine (lpc3154 only) ? 8/16-bit multi-port memory co ntroller (mpmc): sdram and sram ? security ? aes decryption engine (lpc3154 only) ? secure one-time programma ble memory for aes key st orage and customer use ? 128 bit unique id per device for drm schemes ? communication and connectivity ? high-speed usb 2.0 (otg, host, device) with on-chip phy ? two i 2 s-bus interfaces ? integrated master/slave spi ? two master/slave i 2 c-bus interfaces ? fast uart ? memory card interface (mci): mmc/sd/sdio/ce-ata lpc3152/3154 arm926ej microcontrollers wit h usb high-speed otg, sd/mmc, nand flash contro ller, and audio codec rev. 0.12 ? 27 may 2010 preliminary data sheet
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 2 of 88 nxp semiconductors lpc3152/3154 ? three-channel 10-bit adc ? integrated 4/8/16-bit 6800/8080 compatible lcd interface ? integrated audio codec with stereo adc and class ab headphone amplifier ? system functions ? dynamic clock gating and scaling ? multiple power domains ? selectable boot-up: spi flash, nand fl ash, sd/mmc cards, uart, or usb ? on the lpc3154 only: secure booting using aes decryption engine from spi flash, nand flash, sd/mmc cards, uart, or usb ? dma controller ? four 32-bit timers ? watchdog timer ? pwm module ? master/slave pcm interface ? random number generator (rng) ? general purpose i/o (gpio) pins ? flexible and versatile interrupt structure ? jtag interface with boundary scan and arm debug access ? real-time clock (rtc) ? power supply ? integrated power supply unit ? li-ion charger ? usb charge pump ? operating voltage and temperature ? core voltage: 1.2 v ? i/o voltage: 1.8 v, 3.3 v ? temperature: ? 40 c to +85 c ? tfbga208 package: 12 12 mm 2 , 0.7 mm pitch 3. ordering information table 1. ordering information type number package name description version lpc3152fet208 tfbga208 tfbga208: plastic thin fine-pitch ball grid array package; 208 balls; body 12 x 12 x 0.7 mm sot930-1 lpc3154fet208 tfbga208 tfbga208: plastic thin fine-pitch ball grid array package; 208 balls; body 12 x 12 x 0.7 mm sot930-1
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 3 of 88 nxp semiconductors lpc3152/3154 3.1 ordering options table 2. ordering options for lpc3152/54 type number total sram nand flash controller security engine aes high-speed usb 10-bit adc channels audio codec, psu, rtc, li-ion charger mci sdhc/ sdio/ ce-ata pins temperature range lpc3152fet208 192 kb yes no device/ host/otg 3 yes yes 208 ? 40 c to +85 c lpc3154fet208 192 kb yes yes device/ host/otg 3 yes yes 208 ? 40 c to +85 c
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 4 of 88 nxp semiconductors lpc3152/3154 4. block diagram (1) aes decryption engine available in lpc3154 only. fig 1. lpc3152/3154 block diagram 96 kb isram0 arm926ej-s test/debug interface dma mci sd/sdio usb 2.0 high-speed otg ahb to apb bridge 0 jtag wdt system control cgu ioconfig 10-bit adc rng event router otp lpc3152/3154 master master master master slave 002aae095 slave ahb to apb bridge 1 i 2 c1 pwm i 2 c0 timer 0/1/2/3 slave nand registers dma registers ahb to apb bridge 4 slave slave 96 kb isram1 slave slave rom interrupt controller slave slave slave slave slave multi-layer ahb matrix data cache 16 kb instruction cache 16 kb uart lcd spi pcm ahb to apb bridge 2 mpmc i 2 s0 ahb to apb bridge 3 slave slave i 2 s1 rtc psu li-ion charger analog die audio codec usb charge pump nand controller buffer aes (1)
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 5 of 88 nxp semiconductors lpc3152/3154 5. pinning information 5.1 pinning fig 2. lpc3152/3154 pinning tfbga208 package 002aae464 lpc3152/ lpc3154 transparent top view ball a1 index area u t r p n m k h l j g f e d c a b 24681012 13 14 15 17 16 1357911 table 3. pin allocation table pin names with prefix m are multiplexed pins. see table 11 for pin function selection of multiplexed pins. pin symbol pin symbol pin symbol pin symbol row a 1 n.c. 2 ebi_a_1_cle 3 ebi_d_9 4 vdde_ioc 5 vsse_ioc 6 vddi 7 vssi 8 spi_miso 9 i2c_scl0 10 ffast_in 11 n.c. 12 n.c. 13 adc10b_gnda 14 vsse_ioc 15 vdde_ioc 16 hp_vdda33 17 n.c. - - - row b 1 n.c. 2 n.c. 3 n.c. 4 n.c. 5 mnand_rybn0 6 mgpio9 7 mgpio6 8 spi_mosi 9 n.c. 10 ffast_out 11 vdda12 12 adc10b_gpa0 13 adc10b_vdda33 14 n.c. 15 hp_fcr 16 hp_gnda 17 hp_outl - - - row c 1 n.c. 2 ebi_d_10 3 n.c. 4 ebi_a_0_ale 5 mnand_rybn1 6 mgpio10 7 mgpio7 8 spi_sck 9 vpp 10 i2c_sda0 11 vssa12 12 adc10b_gpa2 13 adc10b_gpa1 14 dac_vdda33 15 hp_outr 16 hp_fcl 17 psu_play - - - row d 1 vdde_ioa 2 ebi_d_11 3 ebi_d_8 4 mnand_rybn3
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 6 of 88 nxp semiconductors lpc3152/3154 5 mnand_rybn2 6 mgpio8 7 mgpio5 8 spi_cs_out0 9 spi_cs_in 10 pwm_data 11 gpio4 12 gpio3 13 n.c. 14 hp_outc 15 psu_stop 16 psu_vssa 17 psu_vssa_clean - - - row e 1 vsse_ioa 2 ebi_d_12 3 ebi_d_7 4 ebi_d_6 14 hp_vref 15 rstin_n 16 psu_vbat 17 psu_vout3 row f 1 n.c. 2 ebi_d_13 3 ebi_d_5 4 ebi_d_4 14 tdo 15 dac_vrefn 16 dac_vrefp 17 psu_vbat2 row g 1 n.c. 2 ebi_d_14 3 n.c. 4 ebi_d_3 14 psu_vout2 15 vdde_iod 16 psu_vin1 17 psu_lx2 row h 1 vssi 2 ebi_d_15 3 ebi_d_1 4 ebi_d_2 14 psu_vout1 15 psu_lx1 16 psu_vss1 17 psu_vbat1 row j 1 vddi 2 ebi_ncas_blout_0 3 ebi_d_0 4 ebi_nras_blout_1 14 charge_vbus 15 charge_vss 16 psu_vbus 17 charge_vntc row k 1 vsse_iob 2 n.c. 3 ebi_dqm_0_noe 4 ebi_nwe 14 rtc_backup 15 charge_cc_ref 16 charge_vbat 17 charge_bat_sense row l 1 vdde_iob 2 nand_ncs_0 3 nand_ncs_1 4 nand_ncs_2 14 vsse_iod 15 rtc_vdd36 16 fslow_out 17 fslow_in row m 1 vdde_ioa 2 nand_ncs_3 3 n.c. 4 clock_out 14 vddi_ad 15 vssi_ad 16 rtc_int 17 rtc_vss row n 1 vsse_ioa 2 usb_vdda12_pll 3 usb_vbus 4 usb_rref 14 adc_vdda33 15 adc_vdda18 16 adc_gnda 17 uos_vss row p 1 n.c. 2 usb_vssa_ref 3 usb_id 4 mlcd_db_10 5 mlcd_db_9 6 mlcd_db_5 7 mlcd_e_rd 8 mlcd_db_1 9 i2srx_data0 10 uart_txd 11 muart_cts_n 12 gpio2 13 adc_tinl 14 adc_tinr 15 uos_vbus 16 uos_vbat 17 uos_cx2 - - - row r 1 usb_dm 2 usb_vssa_term 3 usb_vdda33 4 mlcd_db_15 5 mlcd_db_6 6 mlcd_db_3 7 mlcd_rs 8 mlcd_csb table 3. pin allocation table ?continued pin names with prefix m are multiplexed pins. see table 11 for pin function selection of multiplexed pins. pin symbol pin symbol pin symbol pin symbol
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 7 of 88 nxp semiconductors lpc3152/3154 9 i2srx_ws0 10 uart_rxd 11 muart_rts_n 12 mi2stx_ws0 13 gpio0 14 adc_vinr 15 adc_mic 16 adc_vrefn 17 uos_cx1 - - - row t 1 usb_dp 2 usb_gnda 3 usb_vdda33_drv 4 mlcd_db_12 5 mlcd_db_7 6 mlcd_db_2 7 mlcd_db_0 8 mlcd_rw_wr 9 i2srx_bck0 10 tdi 11 mi2stx_clk0 12 mi2stx_bck0 13 mi2stx_data0 14 gpio1 15 adc_vinl 16 adc_vref 17 adc_vrefp - - - row u 1 n.c. 2 mlcd_db_14 3 mlcd_db_13 4 mlcd_db_11 5 mlcd_db_8 6 mlcd_db_4 7 vdde_iob 8 vsse_iob 9 tms 10 jtagsel 11 trst_n 12 tck 13 vddi 14 vssi 15 vdde_ioc 16 vsse_ioc 17 rtc_clk32 - - - table 3. pin allocation table ?continued pin names with prefix m are multiplexed pins. see table 11 for pin function selection of multiplexed pins. pin symbol pin symbol pin symbol pin symbol table 4. pin description pin names with prefix m are multiplexed pins. see table 11 for pin function selection of multiplexed pins. tfbga pin name tfb ga ball digital i/o level [1] application function pin state after reset [2] cell type [3] description clock generation unit ffast_in a10 sup1 ai aio2 12 mhz oscillator clock input ffast_out b10 sup1 ao aio2 12 mhz oscillator clock output vdda12 b11 sup1 supply ps3 12 mhz oscillator/plls analog supply vssa12 c11 - ground cg1 12 mhz oscillator/plls analog ground rstin_n e15 sup3 di i:pu dio2 system reset input (active low) clock_out m4 sup4 do o dio4 clock output 10-bit adc adc10b_vdda33 b13 sup3 supply ps3 10-bit adc analog supply adc10b_gnda a13 - ground cg1 10-bit adc analog ground adc10b_gpa0 b12 sup3 ai aio1 10-bit adc analog input adc10b_gpa1 c13 sup3 ai aio1 10-bit adc analog input adc10b_gpa2 c12 sup3 ai aio1 10-bit adc analog input audio adc adc_mic r15 - ai aio2 adc microphone input adc_vinl t15 - ai aio2 adc line input left adc_vinr r14 - ai aio2 adc line input right adc_tinl p13 - ai aio2 adc tuner input left adc_tinr p14 - ai aio2 ad c tuner input right adc_vref t16 - ao aio2 adc reference voltage output
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 8 of 88 nxp semiconductors lpc3152/3154 adc_vrefn r16 - ai aio2 adc negative reference voltage adc_vrefp t17 - ai aio2 adc positive reference voltage adc_vdda18 n15 sup2 supply cs1 adc digital voltage supply adc_vdda33 n14 sup3 supply cs1 adc analog voltage supply adc_gnda n16 - ground cg1 adc analog ground audio stereo dac dac_vdda33 c14 sup3 supply cs1 sdac analog supply dac_vrefp f16 sup3 ai aio2 sdac positive reference voltage dac_vrefn f15 - ai aio2 sdac negative reference voltage class ab amplifier hp_outc d14 - ao aio2 headphone common output reference for class ab hp_fcl c16 - ai aio2 headphone filter capacitor left hp_fcr b15 - ai aio2 headphone filter capacitor right hp_vref e14 - ai aio2 analog reference supply for headphone and dac hp_outl b17 - ao aio2 headphone left output hp_outr c15 - ao aio2 headphone right output hp_vdda33 a16 sup3 supply cs1 headphone analog supply class ab hp_gnda b16 - ground cg1 headphone analog ground usb hs 2.0 otg usb_vbus n3 sup5 ai aio3 usb supply detection line usb_id p3 sup3 ai aio1 indicates to the usb transceiver whether in device (usb_id high) or host (usb_id low) mode (contains internal pull-up resistor) usb_rref n4 sup3 aio aio1 usb connection for external reference resistor (12 k +/- 1%) to analog ground supply usb_dp t1 sup3 aio aio1 usb d+ co nnection with integrated 45 termination resistor usb_dm r1 sup3 aio aio1 usb d ? connection with integrated 45 termination resistor usb_vdda12_pll n2 sup1 supply ps3 usb pll supply usb_vdda33_drv t3 sup3 supply ps3 usb analog supply for driver usb_vdda33 r3 sup3 supply ps3 usb analog supply for phy usb_vssa_term r2 - ground cg1 usb analog ground for clean reference for on chip termination resistors usb_gnda t2 - ground cg1 usb analog ground usb_vssa_ref p2 - ground cg1 usb analog ground for clean reference table 4. pin description ?continued pin names with prefix m are multiplexed pins. see table 11 for pin function selection of multiplexed pins. tfbga pin name tfb ga ball digital i/o level [1] application function pin state after reset [2] cell type [3] description
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 9 of 88 nxp semiconductors lpc3152/3154 jtag jtagsel u10 sup3 di / gpio i:pd dio1 jtag selection. controls which digital die tap controller is confi gured in the jtag chain along with the analog die tap controller. must be low during power-on reset. tdi t10 sup3 di / gpio i:pu dio1 jtag data input trst_n u11 sup3 di / gpio i:pd dio1 jtag t ap controller reset input. must be low during power-on reset. tck u12 sup3 di / gpio i:pd dio1 jtag clock input tms u9 sup3 di / gpio i:pu dio1 jtag mode select input tdo f14 sup3 do z dio2 jtag data output uart muart_cts_n [4] [6] p11 sup3 di / gpio i dio1 uart clear-to-send (cts) (active low) muart_rts_n [4] [6] r11 sup3 do / gpio o dio1 uart ready-to-send (rts) (active low) uart_rxd [4] r10 sup3 di / gpio i dio1 uart serial input uart_txd [4] p10 sup3 do / gpio o dio1 uart serial output i 2 c master/slave interface i2c_sda0 c10 sup3 dio i iicd i 2 c-bus data line i2c_scl0 a9 sup3 dio i iicc i 2 c-bus clock line serial peripheral interface (spi) spi_cs_out0 [4] d8 sup3 do o dio4 spi chip select output (master) spi_sck [4] c8 sup3 dio i dio4 spi clock input (s lave) / clock output (master) spi_miso [4] a8 sup3 dio i dio4 spi data input (master) / data output (slave) spi_mosi [4] b8 sup3 dio i dio4 spi data output (master) / data input (slave) spi_cs_in [4] d9 sup3 di i dio4 spi chip select input (slave) digital power supply vddi j1; u13; a6 sup1 supply cs2 digital core supply vddi_ad m14 sup2 supply cs2 core supply for digital logic on analog die - has to be connected to 1.4/1.8 v rail vssi h1; u14; a7 - ground cg2 digital core ground vssi_ad m15 - ground cg2 digital co re ground of analog die peripheral power supply vdde_ioa d1; m1 sup4 supply ps1 peripheral supply nand flash controller vdde_iob l1; u7 sup8 supply ps1 peripheral supply lcd interface / sdram interface table 4. pin description ?continued pin names with prefix m are multiplexed pins. see table 11 for pin function selection of multiplexed pins. tfbga pin name tfb ga ball digital i/o level [1] application function pin state after reset [2] cell type [3] description
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 10 of 88 nxp semiconductors lpc3152/3154 vdde_ioc u15; a15; a4; sup3 supply ps1 peripheral supply vdde_iod g15 sup3 supply ps2 analog die peripheral supply vsse_ioa e1; n1 - ground pg1 peripheral ground nand flash controller vsse_iob k1; u8 - ground pg1 peripheral ground lcd interface / sdram interface vsse_ioc u16; a14; a5; - ground pg1 peripheral ground vsse_iod l14 - ground pg2 analog die peripheral ground lcd interface mlcd_csb [4] r8 sup8 do o dio4 lcd chip select (active low) mlcd_e_rd [4] p7 sup8 do o dio4 lcd: 6800 enable, 8080 read enable (active high) mlcd_rs [4] r7 sup8 do o dio4 lcd: instruction r egister (low)/ data register (high) select mlcd_rw_wr [4] t8 sup8 do o dio4 lcd: 6800 read /write select,8080 write enable (active high) mlcd_db_0 [4] t7 sup8 dio o dio4 lcd data 0 mlcd_db_1 [4] p8 sup8 dio o dio4 lcd data 1 mlcd_db_2 [4] t6 sup8 dio o dio4 lcd data 2 mlcd_db_3 [4] r6 sup8 dio o dio4 lcd data 3 mlcd_db_4 [4] u6 sup8 dio o dio4 lcd data 4 mlcd_db_5 [4] p6 sup8 dio o dio4 lcd data 5 mlcd_db_6 [4] r5 sup8 dio o dio4 lcd data 6 mlcd_db_7 [4] t5 sup8 dio o dio4 lcd data 7 mlcd_db_8 [4] u5 sup8 dio o dio4 lcd data 8 / 8-bit data 0 mlcd_db_9 [4] p5 sup8 dio o dio4 lcd data 9 / 8-bit data 1 mlcd_db_10 [4] p4 sup8 dio o dio4 lcd data 10 / 8-bit data 2 mlcd_db_11 [4] u4 sup8 dio o dio4 lcd data 11 / 8-bit data 3 mlcd_db_12 [4] t4 sup8 dio o dio4 lcd data 12 / 8-bit data 4 / 4-bit data 0 mlcd_db_13 [4] u3 sup8 dio o dio4 lcd data 13 / 8-bit data 5 / 4-bit data 1 / serial clock output mlcd_db_14 [4] u2 sup8 dio o dio4 lcd data 14 / 8-bit data 6 / 4-bit data 2 / serial data input mlcd_db_15 [4] r4 sup8 dio o dio4 lcd data 15 / 8-bit data 7 / 4-bit data 3 / serial data output i 2 s/digital audio input i2srx_data0 [4] p9 sup3 di / gpio i dio1 i 2 s input serial data receive table 4. pin description ?continued pin names with prefix m are multiplexed pins. see table 11 for pin function selection of multiplexed pins. tfbga pin name tfb ga ball digital i/o level [1] application function pin state after reset [2] cell type [3] description
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 11 of 88 nxp semiconductors lpc3152/3154 i2srx_bck0 [4] t9 sup3 dio / gpio i dio1 i 2 s input bitclock i2srx_ws0 [4] r9 sup3 dio / gpio i dio1 i 2 s input word select i 2 s/digital audio output mi2stx_data0 [4] t13 sup3 do / gpio o dio1 i 2 s output serial data out mi2stx_bck0 [4] t12 sup3 do / gpio o dio1 i 2 s output bitclock mi2stx_ws0 [4] r12 sup3 do / gpio o dio1 i 2 s output word select mi2stx_clk0 [4] t11 sup3 do / gpio o dio1 i 2 s output serial clock general purpose io (ioconfig module) gpio0 [8] r13 sup3 gpio i:pd dio1 general purpose io pin 0 (mode pin 0) gpio1 [8] t14 sup3 gpio i:pd dio1 general purpose io pin 1 (mode pin 1) gpio2 [8] p12 sup3 gpio i dio1 general purpose io pin 2 (mode pin 2/blinking led) gpio3 d12 sup3 gpio i dio1 general purpose io pin 3 (connect to psu_stop) [5] gpio4 d11 sup3 gpi i dio1 general purpose input pin 4 mgpio5 [4] d7 sup3 gpio i dio4 general purpose io pin 5 mgpio6 [4] b7 sup3 gpio i dio4 general purpose io pin 6 mgpio7 [4] c7 sup3 gpio i dio4 general purpose io pin 7 mgpio8 [4] d6 sup3 gpio i dio4 general purpose io pin 8 mgpio9 [4] b6 sup3 gpio i dio4 general purpose io pin 9 mgpio10 [4] c6 sup3 gpio i dio4 general purpose io pin 10 external bus interface (nand flash controller) ebi_a_0_ale [4] c4 sup4 do o dio4 ebi address latch enable (ale) ebi_a_1_cle [4] a2 sup4 do o dio4 ebi command latch enable (cle) ebi_d_0 [4] j3 sup4 dio i dio4 ebi data i/o 0 ebi_d_1 [4] h3 sup4 dio i dio4 ebi data i/o 1 ebi_d_2 [4] h4 sup4 dio i dio4 ebi data i/o 2 ebi_d_3 [4] g4 sup4 dio i dio4 ebi data i/o 3 ebi_d_4 [4] f4 sup4 dio i dio4 ebi data i/o 4 ebi_d_5 [4] f3 sup4 dio i dio4 ebi data i/o 5 ebi_d_6 [4] e4 sup4 dio i dio4 ebi data i/o 6 ebi_d_7 [4] e3 sup4 dio i dio4 ebi data i/o 7 ebi_d_8 [4] d3 sup4 dio i dio4 ebi data i/o 8 ebi_d_9 [4] a3 sup4 dio i dio4 ebi data i/o 9 ebi_d_10 [4] c2 sup4 dio i dio4 ebi data i/o 10 ebi_d_11 [4] d2 sup4 dio i dio4 ebi data i/o 11 ebi_d_12 [4] e2 sup4 dio i dio4 ebi data i/o 12 ebi_d_13 [4] f2 sup4 dio i dio4 ebi data i/o 13 table 4. pin description ?continued pin names with prefix m are multiplexed pins. see table 11 for pin function selection of multiplexed pins. tfbga pin name tfb ga ball digital i/o level [1] application function pin state after reset [2] cell type [3] description
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 12 of 88 nxp semiconductors lpc3152/3154 ebi_d_14 [4] g2 sup4 dio i dio4 ebi data i/o 14 ebi_d_15 [4] h2 sup4 dio i dio4 ebi data i/o 15 ebi_dqm_0_noe [4] k3 sup4 do o dio4 ebi read enable (active low) ebi_nwe [4] k4 sup4 do o dio4 ebi wr ite enable (active low) nand_ncs_0 [4] l2 sup4 do o dio4 ebi chip enable 0 nand_ncs_1 [4] l3 sup4 do o dio4 ebi chip enable 1 nand_ncs_2 [4] l4 sup4 do o dio4 ebi chip enable 2 nand_ncs_3 [4] m2 sup4 do o dio4 ebi chip enable 3 mnand_rybn0 [4] b5 sup4 di i dio4 ebi nand ready/busy 0 mnand_rybn1 [4] c5 sup4 di i dio4 ebi nand ready/busy 1 mnand_rybn2 [4] d5 sup4 di i dio4 ebi nand ready/busy 2 mnand_rybn3 [4] d4 sup4 di i dio4 ebi nand ready/busy 3 ebi_ncas_blout_0 [4] j2 sup4 do o dio4 ebi lower lane byte select (7:0) ebi_nras_blout_1 [4] j4 sup4 do o dio4 ebi upper lane byte select (15:8) secure one time programmable memory vpp [7] c9 sup1/ sup3 supply ps3 supply for polyfuse programming real time clock (rtc) rtc_vdd36 l15 sup6 supply cs1 rtc supply connected to battery rtc_vss m17 - ground cg1 rtc ground fslow_out l16 sup7 ao aio2 rtc 32.768 khz clock output fslow_in l17 sup7 ai aio2 rtc 32.768 khz clock input rtc_int m16 sup6 do o aio2 rtc interrupt (high active) rtc_backup k14 sup7 supply cs1 rtc backup capacitor connection rtc_clk32 u17 sup6 ao o aio2 rtc 32 khz clock output for on-board applications such as tuner power supply unit psu_vbus j16 sup5 supply cs1 ps u usb supply voltage psu_vout1 h14 sup3 ao cs1 psu output1 psu_lx1 h15 - aio cs1 psu external coil terminal for output1 psu_lx2 g17 - aio cs1 psu external coil terminal for output2 psu_vss1 h16 - ground cg1 psu ground psu_vin1 g16 - ai cs1 psu output1 input voltage psu_vout2 g14 sup1 ao cs1 psu output2 psu_vout3 e17 sup2 ao cs1 psu output3 psu_vssa d16 - ground cg1 psu ground psu_vssa_clean d17 - ground cg1 psu reference circuit ground psu_play c17 sup3 ai i aio2 psu play button input (active high) table 4. pin description ?continued pin names with prefix m are multiplexed pins. see table 11 for pin function selection of multiplexed pins. tfbga pin name tfb ga ball digital i/o level [1] application function pin state after reset [2] cell type [3] description
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 13 of 88 nxp semiconductors lpc3152/3154 [1] digital io levels are explained in ta b l e 5 . [2] i = input; i:pu = input with internal weak pull-up; i:pd = input with internal weak pull-down; o = output. [3] cell types are explained in table 6 . [4] pin can be configured as gpio pin in the ioconfig block. [5] gpio3 is driven high if the boot process fails. it is reco mmended to connect gpio3 to psu_stop, so that the lpc3152/3154 wil l be powered down and further access prevented if the boot rom detects an error. [6] the uart flow control lines (muart_cts_n and muart_rts_n) are multiplexed. this means that if these balls are not required f or uart flow control, they can be selected to be used for their alternative function: spi chip select signals (spi_cs_out1 and spi_cs_out2). [7] the polyfuses get unintent ionally burned at random if vpp is powered to 2.3 v or greater before the vddi is powered up to mi nimum nominal voltage. this will destroy the sample, and it can be lo cked (security) and the aes key can be corrupted. for this reason it is recommended that vpp be powered by sup1 at power-on. [8] to ensure that gpio0, gpio1 and gpio2 pi ns come up as inputs, pins trst_n and jtagsel must be low at power-on reset, see um10315 jtag chapter for details. psu_stop d15 sup3 aio i aio2 psu stop signal input (active high) psu_vbat1 h17 sup6 supply cs1 psu dcdc1 supply input psu_vbat2 f17 sup6 supply cs1 psu dcdc2 supply input psu_vbat e16 sup6 supply cs1 psu li-ion battery input li-ion charger charge_vntc j17 - ai aio2 charger ntc connection charge_vss j15 - ground cg1 charger ground li-ion charge_cc_ref k15 - ao cs1 charger constant current reference charge_vbus j14 sup5 supply cs1 charger 5 v supply charge_bat_sense k17 - ai aio2 charger battery sense terminal charge_vbat k16 sup6 ao cs1 charger positive battery terminal connection usb charge pump (host mode) uos_vss n17 - ground cg1 usb charge pump ground uos_vbus p15 sup5 ao cs1 usb char ge pump output to usb_vbus uos_vbat p16 sup6 supply cs1 usb charge-pump supply li-ion battery input uos_cx2 p17 - aio cs1 usb charge-pump capacitor terminal for voltage converter uos_cx1 r17 - aio cs1 usb charge-pump capacitor terminal for voltage converter pulse width modulation module pwm_data [4] d10 sup3 do/gpio o dio1 pwm output table 4. pin description ?continued pin names with prefix m are multiplexed pins. see table 11 for pin function selection of multiplexed pins. tfbga pin name tfb ga ball digital i/o level [1] application function pin state after reset [2] cell type [3] description
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 14 of 88 nxp semiconductors lpc3152/3154 [1] when the sdram is used, the supply voltage of the nand flash, s dram, and the lcd interface must be the same, i.e. sup4 and sup8 should be connected to the same rail. (see also section 6.28.3 .). table 5: supply domains supply domain voltage range related supply pins description sup1 1.0 v to 1.3 v vddi, vdda12, usb_vdda12_pll, vpp (read) digital core supply sup2 1.4 v or 1.8 v vddi_ad, adc_vdda18 digital core supply for the analog die functions sup3 2.7 v to 3.6 v vdde_ioc, vdde_iod, adc10b_vdda33, adc_vdda33, dac_vdda33, hp_vdda33, usb_vdda33_drv, usb_vdda33, vpp (write) peripheral supply sup4 1.65 v to 1.95 v (in 1.8 v mode) 2.5 v to 3.6 v (in 3.3 v mode) vdde_ioa peripheral supply for nand flash interface sup5 4.5 v to 5.5 v psu _vbus, charge_vbus, uos_vbus, usb_vbus usb vbus voltage sup6 3.2 v to 4.2 v rtc_vdd36, psu_vbat1, psu_vbat2, psu_vbat li-ion battery voltage sup7 1.8 v rtc_backup real-time clock voltage domain (generated internally from sup6) sup8 1.65 v to 1.95 v (in 1.8 v mode) 2.5 v to 3.6 v (in 3.3 v mode) vdde_iob peripheral supply for sdram/sram/bus-based lcd [1] table 6: cell types i/o pad name type function description dio1 bspts3chp digital input/output bidirectional 3.3 v; 3-state output; 3 ns slew rate control; plain input; cmos with hysteresis; programmable pull-up, pull-down, repeater. dio2 bpts5pcph digital input/output bidirectional 5 v; plain input; 3-state output; cmos with programmable hysteresis; programmable pull-up, pull-down, repeater. dio3 bpts5pcph1v8 digital input/output bidirectional 1. 8 v; plain input; 3-state output; cmos with programmable hysteresis; programmable pull-up, pull-down, repeater. dio4 mem1 bsptz40pchp digital input/output bidirectional 1.8 or 3.3 v; plain input; 3-state output; cmos with programmable hysteresis; programmable pull-up, pull-down, repeater. iicc iic3m4scl digital input/output i 2 c-bus; clock signal; cell based esd protection. iicd iic3mvsda digital input/output i 2 c-bus; data signal; cell based esd protection. aio1 apio3v3 analog input/output analog cell; analo g input/output; protection to external 3.3 v supply rail. aio2 apio analog input/output analog pad; analog input/output. aio3 apiot5v analog input/output analog cell; ana log input/output; 5 v tolerant pad-based esd protection. cs1 vddco core supply - cs2 vddi core supply -
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 15 of 88 nxp semiconductors lpc3152/3154 6. functional description 6.1 arm926ej-s the processor embedded in the chip is the arm926ej-s. it is a member of the arm9 family of general-purpose microprocessors. the arm926ej-s is intended for multi-tasking applications where full memory management, high performance, and low power are important. this module has the following features: ? arm926ej-s processor core which uses a fi ve-stage pipeline consisting of fetch, decode, execute, memory and write stages. the processor supports both the 32-bit arm and 16-bit thumb instruction sets, which allows a trade off between high performance and high code density. the arm926ej-s also executes an extended armv5te instruction set which includes support for java byte code execution. ? contains an amba biu for both data accesses and instruction fetches. ? memory management unit (mmu). ? 16 kb instruction and 16 kb data separate cache memories with an 8 word line length. the caches are organized us ing harvard architecture. ? little endian is supported. ? the arm926ej-s processor supports the arm debug architecture and includes logic to assist in both hardware and software debugging. ? supports dynamic clock gating for power reduction. ? the processor core clock can be set equal to the ahb bus clock or to an integer number times the ahb bus clock. the pr ocessor can be switched dynamically between these settings. ? arm stall support. ps1 vdde3v3 peripheral supply - ps2 vdde peripheral supply - cg1 vssco core ground - cg2 vssis core ground - pg1 vsse peripheral ground - table 6: cell types i/o pad name type function description
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 16 of 88 nxp semiconductors lpc3152/3154 6.2 memory map 6.2.1 analog die memory organization the blocks on the analog die (audio codec, rt c, li-ion charger, and power supply unit (psu)) and their registers are accessed through the i 2 c1-bus interface as a single slave device with device address 0x0c using the following register addresses: (1) aes is available on the lpc3154 only. fig 3. lpc3152/3154 memory map 0x0000 0000 0x0000 1000 0 gb 2 gb 4 gb 0x1102 8000 0x1104 0000 0x1105 8000 0x1200 0000 0x1202 0000 0x1300 0000 0x1300 8000 0x1300 b000 0x1500 0000 0x1600 0000 reserved 96 kb isram0 96 kb isram1 128 kb rom reserved reserved reserved reserved reserved external sram bank 0 external sram bank 1 external sdram bank 0 reserved reserved apb0 domain apb1 domain apb2 domain apb3 domain 0x1700 0000 0x1700 8000 0x1700 9000 0x1800 0000 0x1800 0900 0x1900 0000 0x1900 1000 0x2000 0000 0x2002 0000 0x2004 0000 0x3000 0000 0x4000 0000 0x6000 0000 0x6000 1000 0x7000 0000 0x7000 0800 0x8000 0000 0xffff ffff reserved mci/sd/sdio usb otg apb4 domain mpmc configuration registers shadow area lpc3152/3154 interrupt controller nand flash/aes buffer (1) reserved reserved 0x1300 2000 0x1300 2400 0x1300 0000 event router adc 10-bit 0x1300 2800 0x1300 3000 0x1300 4000 0x1300 6000 0x1300 5000 syscreg ioconfig cgu otp rng apb0 domain 0x1500 0400 0x1500 0000 pcm reserved lcd 0x1500 0800 0x1500 1000 0x1500 2000 0x1600 0000 0x1500 3000 reserved uart spi apb2 domain 0x1700 0800 0x1700 0000 dma nand flash controller 0x1700 1000 0x1700 8000 reserved apb4 domain reserved 0x1600 0080 apb3 domain 0x1300 8400 0x1300 8000 timer 0 timer 1 0x1300 8800 0x1300 8c00 0x1300 9000 0x1300 a400 0x1300 b000 0x1300 a000 timer 2 timer 3 pwm i 2 c0 i 2 c1 apb1 domain reserved 002aae100 i 2 s system config 0x1600 0100 i2stx_0 0x1600 0180 i2stx_1 0x1600 0200 i2srx_0 0x1600 0280 i2srx_1 wdt
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 17 of 88 nxp semiconductors lpc3152/3154 6.3 jtag the jtag interface allows the incorporation of the lpc3152/3154 in a jtag scan chain. this module has the following features: ? arm926 debug access ? boundary scan ? the arm926 debug access can be permanently disabled through the jtag security bits in the one-time programmable memory (otp) block. 6.4 nand flash controller the nand flash controller is used as a dedi cated interface to nand flash devices. figure 4 shows a block diagram of the nand flash controller module. the heart of the module is formed by a controller block that co ntrols the flow of data from/to the ahb bus through the nand flash controller block to/fr om the (external) nand flash. an error correction encoder/decoder module allows for hardware error correction for support of multi-level cell (mlc) nand flash devices. in the lpc3154, the nand flash controller is connected to the aes block to support se cure (encrypted) co de execution (see section 6.21 ). before data is written from the buffer to the nand flash, optionally it is first protected by an error correction code generated by the ecc module. after data is read from the nand flash, the error correc tion module corrects errors, and/or the aes decryption module can decrypt data. table 7. analog die register addresses (i 2 c1 slave device address 0x0c) block address offset psu/li-ion charger 0x0000 - 0x000f audio codec 0x0010 - 0x001f rtc 0x0020 - 0x002f
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 18 of 88 nxp semiconductors lpc3152/3154 this module has the following features: ? dedicated nand flash interface with hard ware controlled read and write accesses. ? wear leveling support with 516-byte mode. ? software controlled command and address transfers to support wide range of flash devices. ? software control mode where the arm is directly master of the flash device. ? support for 8-bit and 16-bit flash devices. ? support for any page size from 0.5 kb upwards. ? programmable nand flash timing parameters. ? support for up to four nand devices. ? hardware aes decrypti on (lpc3154 only). ? error correction module (ecc) for mlc nand flash support: ? reed-solomon error correction encoding and decoding. ? uses reed-solomon code words with 9-bit symbols over gf(2 9 ), a total code word length of 469 symbols, including 10 pa rity symbols, giving a minimum hamming distance of 11. ? up to 8 symbol errors can be corrected per codeword. ? error correction can be turned on and off to match the demands of the application. ? parity generator for error correction encoding. ? wear leveling information can be integrated into protected data. (1) aes decoder available on lpc3154 only. fig 4. block diagram of the nand flash controller 002aae083 ahb multi-layer matrix buffer controller aes decoder (1) ecc encoder/ decoder nand interface dma transfer request
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 19 of 88 nxp semiconductors lpc3152/3154 ? interrupts generated after completion of error correction task with three interrupt registers. ? error correction statistics distribu ted to arm using interrupt scheme. ? interface is compatible with the arm external bus interface (ebi). 6.5 multi-port memory controller (mpmc) the multi-port memory controller supports the interface to different memory types, for example: ? sdram ? low-power sdram ? static memory interface this module has the following features: ? dynamic memory interface support incl uding sdram, jedec low-power sdram. ? address line supporting up to 128 mb (two 64mx8 devices connected to a single chip select) of dynamic memory. ? the mpmc has two ahb interfaces: a. an interface for accessing external memory. b. a separate control interface to program the mpmc. this enables the mpmc registers to be situated in memory wit h other system peripheral registers. ? low transaction latency. ? read and write buffers to reduce latency an d to improve performance, particularly for un-cached processors. ? static memory features include: ? asynchronous page mode read ? programmable wait states ? bus turnaround delay ? output enable, and write enable delays ? extended wait ? one chip select for synchronous memory and two chip selects for static memory devices. ? power-saving modes. ? dynamic memory self-refresh mode supported. ? controller support for 2 k, 4 k, and 8 k row address synchronous memory parts. ? support for all ahb burst types. ? little and big-endian support. ? support for the external bus interface (ebi) that enables the memory controller pads to be shared.
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 20 of 88 nxp semiconductors lpc3152/3154 6.6 external bus interface (ebi) the ebi module acts as multiplexer with ar bitration between the nand flash and the sdram/sram memory modules connected externally through the mpmc. the main purpose for using the ebi module is to save external pins. however only data and address pins are multiplexed. control signals towards and from the external memory devices are not multiplexed. 6.7 internal rom memory the internal rom memory is used to store the boot code of the lpc3152/3154. after a reset, the arm processor will start its code execution from this memory. the lpc3154 rom memory has the following features: ? supports secure booting fr om spi flash, nand flash, sd/sdhc/mmc cards, uart, and usb (dfu class) interfaces. ? supports sha1 hash checking on the boot image. ? supports un-secure boot from uart and usb (dfu class) interfaces during development. once the aes key is program med in the otp, only secure boot is allowed through uart and usb. ? supports secure booting from managed nand devices such as movinand, inand, emmc-nand and esd-nand using sd/mmc boot mode. ? contains pre-defined mmu table (16 kb) for simple systems. the lpc3152 rom memory has the following features: ? supports non-secure booting from spi flash, nand flash, sd/sdhc/mmc cards, uart, and usb (dfu class) interfaces. ? supports option to perform crc32 checking on the boot image. ? supports non-secure booting from uart and usb (dfu class) interfaces during development. ? supports non-secure booting from managed nand devices such as movinand, inand, emmc-nand and esd-nand using sd/mmc boot mode. ? contains pre-defined mmu table (16 kb) for simple systems. table 8. memory map of the ext ernal sram/sdram memory modules module maximum address space data width device size external sram0 0x2000 0000 0x2000 ffff 8 bit 64 kb 0x2000 0000 0x2001 ffff 16 bit 128 kb external sram1 0x2002 0000 0x2002 ffff 8 bit 64 kb 0x2002 0000 0x2003 ffff 16 bit 128 kb external sdram0 0x3000 0000 0x37ff ffff 16 bit 128 mb
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 21 of 88 nxp semiconductors lpc3152/3154 the boot rom determines the b oot mode based on the reset state of the gpio0, gpio1, and gpio2 pins. to ensure that gpio0, gpio 1 and gpio2 pins come up as inputs, pins trst_n and jtagsel must be low during power-on reset, see um10315 jtag chapter for details. ta b l e 9 shows the various boot modes supported on the lpc3152/3154. if the boot process fails (e.g. due to tamp ering with security), the boot code drives pin gpio3 high. it is recommended to connect the gpio3 pin to psu_stop, so that the lpc3152/3154 will be powered down and further access preven ted when the boot rom detects an error. [1] for security reasons this mode is disa bled when jtag security feature is used. 6.8 internal ram memory the isram (internal static memo ry controller) module is us ed as controller between the ahb bus and the internal ram memory. the internal ram memory can be used as working memory for the arm processor and as temporary storage to execute the code that is loaded by boot rom from external devices such as spi-flash, nand flash and sd/mmc cards. this module has the following features: ? capacity of 192 kb ? implemented as two independent 96 kb memory banks table 9. lpc3152/3154 boot modes boot mode gpio0 gpio1 gpio2 description nand 0 0 0 boots from nand flash. if proper image is not found, boot rom will switch to dfu boot mode. spi 0 0 1 boot from spi nor flash connected to spi_cs_out0. if proper image is not found, boot rom will switch to dfu boot mode. dfu 0 1 0 device boots via usb using dfu class specification. sd/mmc 0 1 1 boot rom searches all the partitions on the sd/mmc/sdhc/mmc+/emmc/es d card for boot image. if partition table is missing, it will start searching from sector 0. a valid image is said to be found if a valid image header is found, followed by a valid image. if a proper image is not found, boot rom will switch to dfu boot mode. reserved 0 1 0 0 reserved for testing. nor flash 1 0 1 boot from parallel nor flash connected to ebi_nstcs_1. [1] uart 1 1 0 boot rom tries to download boot image from uart ((115200 ? 8 ? n ?1) assuming 12 mhz ffast clock). test 1 1 1 boot rom is testing isra m using memory pattern test and basic functionality of the analog audio block. switches to uart boot mode on receiving three asci dots ("...") on uart.
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 22 of 88 nxp semiconductors lpc3152/3154 6.9 memory card interface (mci) the mci controller interface can be used to access memory cards according to the secure digital (sd) and multi-media card (mmc) standards. the host controller can be used to interface to small form factor expansion cards compliant to the sdio card standard as well. finally, the mci supports ce-ata 1.1 compliant hard disk drives. this module has the following features: ? one 8-bit wide interface. ? supports high-speed sd, versions 1.01, 1.10 and 2.0. ? supports sdio version 1.10. ? supports mmcplus, mmcmobile, and mmcmicro cards based on mmc 4.1. ? supports sdhc memory cards. ? crc generation and checking. ? supports 1/4-bit sd cards. ? card detection and write protection. ? fifo buffers of 16 bytes deep. ? host pull-up control. ? sdio suspend and resume. ? 1-byte to 65 535-byte blocks. ? suspend and resume operations. ? sdio read-wait. ? maximum clock speed of 52 mhz (mmc 4.1). ? supports ce-ata 1.1. ? supports 1-bit, 4-bit, and 8-bit mmc cards and ce-ata devices. 6.10 universal serial bus 2. 0 high speed on-the-go (otg) the usb otg module allows the lpc3152/3154 to connect directly to a usb host such as a pc (in device mode) or to a usb device in host mode. in addition, the lpc3152/3154 has a special, built-in mode in which it en umerates as a device firmware upgrade (dfu) class, which allows for a (factory) down load of the device firmware through usb. this module has the following features: ? complies with universal serial bus specification 2.0 . ? complies with usb on-the-go supplement . ? complies with enhanced host controller interface specification . ? supports auto usb 2.0 mode discovery. ? supports all high-speed usb-compliant peripherals. ? supports all full-speed usb-compliant peripherals. ? supports software host ne gotiation protocol (hnp) an d session request protocol (srp) for otg peripherals. ? contains utmi+ compliant transceiver (phy). ? supports interrupts.
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 23 of 88 nxp semiconductors lpc3152/3154 ? this module has its own, integrated dma engine. usb-if testid for hi-speed peripheral s ilicon and embedded host silicon: 40720018 6.11 dma controller the dma controller can perform dma transfers on the ahb bus without using the cpu. this module has the following features: ? supported transfer types: memory to memory copy: ? memory can be copied from the source address to the destination address with a specified length, while incrementing the address for both the source and destination. memory to peripheral: ? data is transferred from incrementing memory to a fixed address of a peripheral. the flow is controlled by the peripheral. peripheral to memory: ? data is transferred from a fixed address of a peripheral to incrementing memory. the flow is controlled by the peripheral. ? supports single data transfers for all transfer types. ? supports burst transfers for memory to memory transfers. a burst always consists of multiples of 4 (32 bit) words. ? the dma controller has 12 channels. ? scatter-gather is used to gather data lo cated at different areas of memory. two channels are needed per scatter-gather action. ? supports byte, half word and word transfers, and correctly aligns it over the ahb bus. ? compatible with arm flow co ntrol, for single requests, last single requests, terminal count info, and dma clearing. ? supports swapping in endianess of the transported data. [1] aes decryption engine is available on lpc3154 only. table 10: peripherals that support dma access peripheral name supported transfer types nand flash controlle r/aes decryption engine [1] memory to memory spi memory to peripheral and peripheral to memory mci memory to peripheral and peripheral to memory lcd interface memory to peripheral uart memory to peripheral and peripheral to memory i 2 c0/1-bus interfaces memory to peripheral and peripheral to memory i 2 s0/1 receive input peripheral to memory i 2 s0/1 transmit output memory to peripheral pcm interface memory to peripheral and peripheral to memory
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 24 of 88 nxp semiconductors lpc3152/3154 6.12 interrupt controller the interrupt controller collects interrupt requests from multip le devices, masks interrupt requests, and forwards the combined requests to the processor. the interrupt controller also provides facilities to identify the in terrupt requesting devices to be served. this module has the following features: ? the interrupt controller decodes all the interrupt requests issued by the on-chip peripherals. ? two interrupt lines (fast interrupt request (fiq) and interrupt re quest (irq)) to the arm core. the arm core supports two distin ct levels of priority on all interrupt sources, fiq for high priority interrupts and irq for normal pr iority interrupts. ? software interrupt request capability associated with each request input. ? visibility of interrupts reque st state before masking. ? support for nesting of interrupt service routines. ? interrupts routed to irq and to fiq are vectored. ? level interrupt support. the following blocks can generate interrupts: ? nand flash controller ? usb 2.0 hs otg ? event router ? 10 bit adc ? uart ? lcd int ? mci ? spi ? i 2 c0-bus and i 2 c1-bus ? timer 0, timer 1, timer 2, and timer 3 ? i 2 s transmit: i2stx_0 and i2stx_1 ? i 2 s receive: i2srx_0 and i2srx_1 ? dma 6.13 multi-layer ahb the multi-layer ahb is an interconnection scheme, based on the ahb protocol that enables parallel access paths between multiple masters and slaves in a system. multiple masters can have access to different slaves at the same time. figure 5 gives an overview of the multi-layer ahb configuration in the lpc3152/3154. ahb masters and slaves are numbered according to their ahb port number.
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 25 of 88 nxp semiconductors lpc3152/3154 this module has the following features: (1) aes decryption engine is available on lpc3154 only. fig 5. lpc3152/3154 ahb multi-layer matrix connections master = master/slave connection supported by matrix 002aae080 usb-otg ahb master 3 0 dma 2 i-cache d-cache 1 arm 926ej-s ahb-apb bridge 0 ahb-apb bridge 1 ahb-apb bridge 3 ahb-apb bridge 4 nand controller interrupt controller pwm i 2 c1 i 2 c0 timer 0 10-bit adc cgu wdt system control ioconfig event router rng otp i 2 s0/1 nand registers dma registers timer 1 timer 2 timer 3 ahb-apb bridge 2 uart lcd spi pcm slave multi-layer ahb matrix 0 1 2 3 4 5 mci sd/sdio 7 usb high-speed otg 8 isram 0 9 isram 1 10 isrom 11 mpmc config mpmc controller 13 12 6 0 0 123 0123 54 67 01 23456 01 aes (1) buffer
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 26 of 88 nxp semiconductors lpc3152/3154 ? supports all combinations of 32-bit masters and slaves (fully connected interconnect matrix). ? round-robin priority mechanism for bus ar bitration: all masters have the same priority and get bus access in their natural order ? four devices on a master port (listed in their natural order for bus arbitration): ? dma ? arm926 instruction port ? arm926 data port ? usb otg ? devices on a slave port (some ports ar e shared between mu ltiple devices): ? ahb to apb bridge 0 ? ahb to apb bridge 1 ? ahb to apb bridge 2 ? ahb to apb bridge 3 ? ahb to apb bridge 4 ? interrupt controller ? nand flash controller ? mci sd/sdio ? usb 2.0 hs otg ? 96 kb isram0 ? 96 kb isram1 ? 128 kb rom ? mpmc (multi-purpose memory controller) 6.14 apb bridge the apb bridge is a bus bridge between amba advanced high-performance bus (ahb) and the arm peripheral bus (apb) interface. the module supports two different architectures: ? single clock architecture, synchronous bridge. the same clock is used at the ahb side and at the apb side of the bridge . the ahb-to-apb4 br idge uses this architecture. ? dual clock architecture, asynchronous bridge. different clocks are used at the ahb side and at the apb side of the br idge. the ahb-to- apb0, ahb-to-apb1, ahb-to-apb2, and ahb-to-apb3 br idges use this architecture. 6.15 clock generation unit (cgu) the clock generation unit generates all clock si gnals in the system and controls the reset signals for all modules. the structure of the cgu is shown in figure 6 . each output clock generated by the cgu belongs to one of the domains. each clock domain is fed by a single base clock that originates from one of the available clock sources. within a clock domain, fractional dividers are available to divide the base clock to a lower frequency.
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 27 of 88 nxp semiconductors lpc3152/3154 within most clock domains, the output clocks are again grouped into one or more subdomains. all output clocks within one subdom ain are either all generated by the same fractional divider or they are connected dire ctly to the base clock. therefore all output clocks within one subdomain have the same frequency and all output clocks within one clock domain are synchronous because they originate from the same base clock the cgu reference clock is generated by the external crystal. furthermore the cgu has several phase locked loop (pll) circuits to g enerate clock signals that can be used for system clocks and/or audio clocks. all clock so urces, except the output of the plls, can be used as reference input for the plls. this module has the following features: ? advanced features to optimize the system for low power: ? all output clocks can be disabled indivi dually for flexible power optimization ? some modules have automatic clock gating: they are only active when (bus) access to the module is required. ? variable clock scaling for au tomatic power optimization of the ahb bus (high clock frequency when the bus is active, low clock frequency when the bus is idle). ? clock wake-up feature: module clocks can be programmed to be activated automatically on the basis of an event detected by the event router (see also section 6.19 ). for example, all clocks (including the arm /bus clocks) are off and activated automatically when a button is pressed. ? supports three clock sources: ? reference clock ge nerated by the oscillator with an external crystal. ? pins i2srx_bck0, i2srx_ws0 are used to input external clock signals (used for generating audio frequencies in i 2 s receive / i 2 s transmit slave mode, see also section 6.4 ). ? two plls: ? system pll generates programmable system clock frequency from its reference input. ? audio pll generates programmable audio clock frequency (typically 256 fs) from its reference input. remark: both the system pll and the audio pll generate their frequencies based on their (individual) referenc e clocks. the refere nce clocks can be programmed to the oscillator clock or one of the exter nal clock signals. ? highly flexible switchbox to distribute the signals from the clock sources to the module clocks. ? each clock generated by the cgu is derived from one of the base clocks and optionally divided by a fractional divider. ? each base clock can be programmed to have any one of the clock sources as an input clock. ? fractional dividers can be used to divide a base clock by a fractional number to a lower clock frequency. ? fractional dividers support clock stretc hing to obtain a (near) 50% duty cycle output clock. ? register interface to reset all modules un der software control.
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 28 of 88 nxp semiconductors lpc3152/3154 ? based on the input of the watchdog timer (see also section 6.16 ), the cgu can generate a system-wide reset in the case of a system stall. 6.16 watchdog timer (wdt) the watchdog timer can be used to generate a system reset if there is a cpu/software crash. in addition the watchdog timer can be used as an ordinary timer. figure 7 shows how the watchdog timer module is connected in the system. this module has the following features: ? in the event of a software or hardware failure, generates a chip-wide reset request when its programmed time-out period has expired (output m1). ? watchdog counter can be reset by a periodical software trigger. ? after a reset, a regist er will indicate whether a rese t has occurred because of a watchdog generated reset. ? watchdog timer can also be used as a normal timer in addition to the watchdog functionality (output m0). the lpc3152/3154 has 11 clock domains (n = 11). the num ber of fractional dividers depends on the clock domain. fig 6. cgu block diagram oscillator i2srx_bck0 i2srx_ws0 base base i 2 s/audio pll external crystal system pll 002aae385 clock domain 0 clock domain n fractional divider 0 fractional divider i fractional divider 6 fractional divider j clock resources clock outputs switchbox subdomain clocks to modules
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 29 of 88 nxp semiconductors lpc3152/3154 6.17 input/output configur ation module (ioconfig) the general purpose input/output (gpio) pins can be controlled through the register interface provided in the ioconfig module. next to several dedica ted gpio pins, most digital io pins can also be used as gpio if they are not required for their normal, dedicated function. this module has the following features: ? provides control for the digital pins that can double as gpio (next to their normal function). the pinning list in ta b l e 4 indicates which pins can double as gpio. ? each controlled pin can be configured for 4 operational modes: ? normal operation (i.e. controlled by a function block). ? driven low. ? driven high. ? high impedance/input. ? a gpio pin can be observed (read) in any mode. ? the register interface provides set and clear access methods for choosing the operational mode. 6.18 10-bit analog-to-digit al converter (adc10b) this module is a 10-bit su ccessive approximation analog-to-digital converter (adc) with an input multiplexer to allow fo r multiple analog signals on it s input. a common use of this module is to read out multiple keys on one input from a resistor network. this module has the following features: ? three analog input channels, selected by an analog multiplexer. a fourth channel is connected internally to the analog die to measure the battery level. ? programmable adc resolution from 2 bit to 10 bit. ? the maximum conversion rate is 400 ksample/s for 10 bit resolution and 1500 ksample/s for 2 bit resolution. ? single a/d conversion scan mode and continuous a/d conversion scan mode. ? power-down mode. fig 7. block diagram of the watchdog timer 002aae086 event router wdt m0 m1 cgu interrupt controller fiq irq reset apb
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 30 of 88 nxp semiconductors lpc3152/3154 6.19 event router the event router extends the interrupt ca pability of the system by offering a flexible and versatile way of generating interrupts. combined with the wake-up functionality of the cgu, it also offers a way to wake-up the system from suspend mode (with all clocks deactivated). the event router has four interrupt outputs connected to the interrupt controller and one wake-up output connected to the cgu as shown in figure 8 . the output signals are activated when an event (for instance a rising edge) is detected on one of the input signals. the input signals of the event router are connected to relevant internal (control) signals in the system or to external signals through pins of the lpc3152/3154. this module has the following features: ? provides programmable routing of input events to multiple outputs for use as interrupts or wake up signals. ? input events can come from internal signals or from the pins that can be used as gpio. ? inputs can be used either directly or latched (edge detected) as an event source. ? the active level (polarity) of the input signal for triggering events is programmable. ? direct events will disappear when the input becomes inactive. ? latched events will remain active un til they are explicitly cleared. ? each input can be masked globally for all inputs at once. ? each input can be masked for each output individually. ? event detect status can be read for each output separately. ? event detection is fully asynchro nous (no active clock required). ? module can be used to generate a system wake-up from suspend mode. remark: all pins that can be used as gpio ar e connected to the event router (see figure 8 ). note that they can be used to trigger events when in normal, functional mode or in gpio mode. fig 8. event router block diagram 002aae087 event router cgu interrupt controller interrupt 0 interrupt 1 interrupt 2 interrupt 3 cgu wakeup apb internal input signals external pins (gpio configurable)
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 31 of 88 nxp semiconductors lpc3152/3154 6.20 random number generator (rng) the random number generator generates true random numbers for use in advanced security and digital rights management (drm) related schemes. these schemes rely upon truly random, i.e. completely unpredictable numbers. this module has the following features: ? true random number generator. ? the random number register does not rely on any kind of reset. ? the generators are free running in order to ensure randomness and security. 6.21 aes decryption (lpc3154 only) this module can be used for data decryption using the aes algorithm. the aes module has the following features: ? aes-128: 128 bit key, 128 bit data. ? cbc mode over blocks of 512 bytes. ? each block of 512 bytes uses the same initial value. ? aes can be turned on and off. 6.22 secure one-time pr ogrammable (otp) memory the otp memory can be used for storing non-volatile information like serial number, security bits, etc. it consists of a polyfuse array, embedded data registers, and control registers. one of the main pur poses of the otp is storing a security key and a unique id. this module has the following features: ? 512-bit, one-time programmable memory ? 128 bit are used for an unique id which is pre-programmed in the wafer fab. ? 40 bit are used for security and other features which are programmed at the customer production line. ? 184 bit are available for customer use. ? 32 bit are used for usb product id and vendor id by boot rom in dfu mode. ? 128 bit are for the secure key used by boot rom to load secure images. remark: on the lpc3152 secure boot is not supported hence these bits are also available for customer use. ? programmable at the customer production line ? random read access via sixteen 32-bit registers ? flexible read protection mechanism to hide security related data ? flexible write protection mechanism 6.23 serial periphe ral interface (spi) the spi module is used for synchronous seri al data communication with other devices which support the spi/ssi protocol. examples of the devices that this spi module can communicate with are memories, cameras, and wifi-g.
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 32 of 88 nxp semiconductors lpc3152/3154 the spi/ssi-bus is a 5-wire interface, and it is suitable for low, medium, and high data rate transfers. this module has the following features: ? supports motorola spi frame format with a word size of 8/16 bits. ? texas instruments ssi (synchronous serial interface) frame format with a word size of 4 bit to 16 bit. ? receive fifo and transmit fifo of 64 half-words each. ? serial clock rate master mode maximum 45 mhz. ? serial clock rate slave mode maximum 25 mhz. ? support for single data access dma. ? full-duplex operation. ? supports up to three slaves. ? supports maskable interrupts. ? supports dma transfers. 6.24 universal asynchronous receiver transmitter (uart) the uart module supports the industry standard serial interface. this module has the following features: ? programmable baud rate with a maximum of 1049 kbd. ? programmable data length (5 bit to 8 bit). ? implements only asynchronous uart. ? transmit break character length indication. ? programmable one to two stops bits in transmission. ? odd/even/force parity check/generation. ? frame error, overrun error and break detection. ? automatic hardware flow control. ? independent control of transmit, receive, line status, data set interrupts, and fifos. ? sir-irda encoder/decoder (from 2400 to 115 kbd). ? supports maskable interrupts. ? supports dma transfers. 6.25 pulse code modulat ion (pcm) interface the pcm interface supports the pcm and iom interfaces. this module has the following features: ? four-wire serial interface. ? can function in both master and slave modes. ? supports: ? mp pcm (multi-protocol pcm): conf igurable directional per slot.
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 33 of 88 nxp semiconductors lpc3152/3154 ? pcm (pulse code modulation): single clocking physical format. ? iom-2 (extended isdn-oriented modular): double clocking physical format. ? twelve 8 bit slots in a frame with enabling control per slot. ? internal frame clock gene ration in master mode. ? receive and transmit dma handshaking using a request/clear protocol. ? interrupt generation per frame. pcm is a very common method used for transmitting analog data in digital format. most common applications of pcm are digital audi o as in audio cds and computers, digital telephony, and digital videos. the iom (isdn oriented modular) interface is primarily used to interconnect telecommunications ics providing isdn compatib ility. it delivers a symmetrical full-duplex communication link containing user data, co ntrol/programming lines, and status channels. 6.26 lcd interface the lcd interface contains logic to interface to a 6800 (motorola) or 8080 (intel) compatible lcd controller which supports 4/8/16 bit modes. this module also supports a serial interface mode. the speed of the interf ace can be adjusted in software to match the speed of the connected lcd display. this module has the following features: ? 4/8/16 bit parallel interface mode: 6800-series, 8080-series. ? serial interface mode. ? supports multiple frequencies for the 6800/8080 bus to support high- and low-speed controllers. ? supports polling the busy flag from lcd c ontroller to off-load the cpu from polling. ? contains an 16 byte fifo for sending control and data information to the lcd controller. ? supports maskable interrupts. ? supports dma transfers. 6.27 i 2 c-bus master/slave interface the lpc3152/3154 contains two i 2 c master/slave interfaces. i 2 c-bus 0 can be used for communicating directly with i 2 c-compatible external devices. i 2 c-bus 1 is internally connected to support the following analog blocks: li-ion charger, power supply unit, rtc, audio adc, audio dac, and class ab amplifier. this module has the following features: ? i 2c0 interface : i 2 c0 is a standard i 2 c-compliant bus interface with open-drain pins. this interface supports functions described in the i 2 c specification for speeds up to 400 khz. this includes multi-master operation and allows powering off this device in a working system while leaving the i 2 c-bus functional. ? i2c1 interface : internally connected to control the functions on the analog die. ? supports normal mode (100 khz scl).
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 34 of 88 nxp semiconductors lpc3152/3154 ? fast mode (400 khz scl with 24 mhz apb clock; 325 khz with1 2 mhz apb clock; 175 khz with 6 mhz apb clock). ? interrupt support. ? supports dma transfers (single). ? four modes of operation: ? master transmitter ? master receiver ? slave transmitter ? slave receiver 6.28 lcd/nand flash/ sdram multiplexing the lpc3152/3154 contains a rich set of spec ialized hardware inte rfaces, but the tfbga package does not contain enough pins to allow use of all signals of all interfaces simultaneously. therefore a pin-multiplexing scheme is implemented, which allows the selection of the right interface for the application. pin multiplexing is enabled between the following interfaces: ? between the dedicated lcd interface an d the external bus interface (ebi). ? between the nand flash controller and the memory card interface (mci). ? between uart and spi. ? between i2stx_0 output and the pcm interface. the pin interface multiplexing is subdivided into five categories: storage, video, audio, nand flash, and uart related pin multiplexi ng. each category supports several modes, which can be selected by programming the corresponding registers in the syscreg. 6.28.1 pin connections table 11. pin descriptions of multiplexed pins pin name default signal alternate signal description video related pin multiplexing mlcd_csb lcd_csb ebi_nstcs_0 lcd_csb ? lcd chip select for external lcd controller. ebi_nstcs_0 ? ebi static memory chip select 0. mlcd_db_1 lcd_db_1 ebi_nstcs_1 lcd_db_1 ? lcd bidirectional data line 1. ebi_nstcs_1 ? ebi static memory chip select 1. mlcd_db_0 lcd_db_0 ebi_clkout lcd_db_0 ? lcd bidirectional data line 0. ebi_clkout ? ebi sdram clock signal. mlcd_e_rd lcd_e_rd ebi_cke lcd_e_rd ? lcd enable/read signal. ebi_cke ? ebi sdram clock enable. mlcd_rs lcd_rs ebi_ndycs lcd_rs ? lcd register select signal. ebi_ndycs ? ebi sdram chip select. mlcd_rw_wr lcd_rw_wr ebi_dqm_1 lcd_rw_wr ? lcd read write/write signal. ebi_dqm_1 ? ebi sdram data mask output 1. mlcd_db_2 lcd_db_2 ebi_a_2 lcd_db_2 ? lcd bidirectional data line 2. ebi_a_2 ? ebi address line 2.
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 35 of 88 nxp semiconductors lpc3152/3154 mlcd_db_3 lcd_db_3 ebi_a_3 lcd_db_3 ? lcd bidirectional data line 3. ebi_a_3 ? ebi address line 3. mlcd_db_4 lcd_db_4 ebi_a_4 lcd_db_4 ? lcd bidirectional data line 4. ebi_a_4 ? ebi address line 4. mlcd_db_5 lcd_db_5 ebi_a_5 lcd_db_5 ? lcd bidirectional data line 5. ebi_a_5 ? ebi address line 5. mlcd_db_6 lcd_db_6 ebi_a_6 lcd_db_6 ? lcd bidirectional data line 6. ebi_a_6 ? ebi address line 6. mlcd_db_7 lcd_db_7 ebi_a_7 lcd_db_7 ? lcd bidirectional data line 7. ebi_a_7 ? ebi address line 7. mlcd_db_8 lcd_db_8 ebi_a_8 lcd_db_8 ? lcd bidirectional data line 8. ebi_a_8 ? ebi address line 8. mlcd_db_9 lcd_db_9 ebi_a_9 lcd_db_9 ? lcd bidirectional data line 9. ebi_a_9 ? ebi address line 9. mlcd_db_10 lcd_db_10 ebi_a_10 lcd_db_10 ? lcd bidirectional data line 10. ebi_a_10 ? ebi address line 10. mlcd_db_11 lcd_db_11 ebi_a_11 lcd_db_11 ? lcd bidirectional data line 11. ebi_a_11 ? ebi address line 11. mlcd_db_12 lcd_db_12 ebi_a_12 lcd_db_12 ? lcd bidirectional data line 12. ebi_a_12 ? ebi address line 12. mlcd_db_13 lcd_db_13 ebi_a_13 lcd_db_13 ? lcd bidirectional data line 13. ebi_a_13 ? ebi address line 13. mlcd_db_14 lcd_db_14 ebi_a_14 lcd_db_14 ? lcd bidirectional data line 14. ebi_a_14 ? ebi address line 14. mlcd_db_15 lcd_db_15 ebi_a_15 lcd_db_15 ? lcd bidirectional data line 15. ebi_a_15 ? ebi address line 15. storage related pin multiplexing mgpio5 gpio5 mci_clk gpio5 ? general purpose i/o pin 5. mci_clk ? mci card clock. mgpio6 gpio6 mci_cmd gpio_6 ? general purpose i/o pin 6. mci_cmd ? mci card command input/output. mgpio7 gpio7 mci_dat_0 gpio7 ? general purpose i/o pin 7. mci_dat_0 ? mci card data input/output line 0. mgpio8 gpio8 mci_dat_1 gpio8 ? general purpose i/o pin 8. mci_dat_1 ? mci card data input/output line 1. mgpio9 gpio9 mci_dat_2 gpio9 ? general purpose i/o pin 9. mci_dat_2 ? mci card data input/output line 2. mgpio10 gpio10 mci_dat_3 gpio10 ? general purpose i/o pin 10. mci_dat_3 ? mci card data input/output line 3. table 11. pin descriptions of multiplexed pins pin name default signal alternate signal description
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 36 of 88 nxp semiconductors lpc3152/3154 mlcd_db_3 lcd_db_3 ebi_a_3 lcd_db_3 ? lcd bidirectional data line 3. ebi_a_3 ? ebi address line 3. mlcd_db_4 lcd_db_4 ebi_a_4 lcd_db_4 ? lcd bidirectional data line 4. ebi_a_4 ? ebi address line 4. mlcd_db_5 lcd_db_5 ebi_a_5 lcd_db_5 ? lcd bidirectional data line 5. ebi_a_5 ? ebi address line 5. mlcd_db_6 lcd_db_6 ebi_a_6 lcd_db_6 ? lcd bidirectional data line 6. ebi_a_6 ? ebi address line 6. mlcd_db_7 lcd_db_7 ebi_a_7 lcd_db_7 ? lcd bidirectional data line 7. ebi_a_7 ? ebi address line 7. mlcd_db_8 lcd_db_8 ebi_a_8 lcd_db_8 ? lcd bidirectional data line 8. ebi_a_8 ? ebi address line 8. mlcd_db_9 lcd_db_9 ebi_a_9 lcd_db_9 ? lcd bidirectional data line 9. ebi_a_9 ? ebi address line 9. mlcd_db_10 lcd_db_10 ebi_a_10 lcd_db_10 ? lcd bidirectional data line 10. ebi_a_10 ? ebi address line 10. mlcd_db_11 lcd_db_11 ebi_a_11 lcd_db_11 ? lcd bidirectional data line 11. ebi_a_11 ? ebi address line 11. mlcd_db_12 lcd_db_12 ebi_a_12 lcd_db_12 ? lcd bidirectional data line 12. ebi_a_12 ? ebi address line 12. mlcd_db_13 lcd_db_13 ebi_a_13 lcd_db_13 ? lcd bidirectional data line 13. ebi_a_13 ? ebi address line 13. mlcd_db_14 lcd_db_14 ebi_a_14 lcd_db_14 ? lcd bidirectional data line 14. ebi_a_14 ? ebi address line 14. mlcd_db_15 lcd_db_15 ebi_a_15 lcd_db_15 ? lcd bidirectional data line 15. ebi_a_15 ? ebi address line 15. storage related pin multiplexing mgpio5 gpio5 mci_clk gpio5 ? general purpose i/o pin 5. mci_clk ? mci card clock. mgpio6 gpio6 mci_cmd gpio_6 ? general purpose i/o pin 6. mci_cmd ? mci card command input/output. mgpio7 gpio7 mci_dat_0 gpio7 ? general purpose i/o pin 7. mci_dat_0 ? mci card data input/output line 0. mgpio8 gpio8 mci_dat_1 gpio8 ? general purpose i/o pin 8. mci_dat_1 ? mci card data input/output line 1. mgpio9 gpio9 mci_dat_2 gpio9 ? general purpose i/o pin 9. mci_dat_2 ? mci card data input/output line 2. mgpio10 gpio10 mci_dat_3 gpio10 ? general purpose i/o pin 10. mci_dat_3 ? mci card data input/output line 3. table 11. pin descriptions of multiplexed pins pin name default signal alternate signal description
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 37 of 88 nxp semiconductors lpc3152/3154 6.28.2 multiplexing between lcd and mpmc the multiplexing between the lcd interface and mpmc a llows for the following two modes of operation: ? mpmc-mode: sdram and bus-based lcd or sram. ? lcd-mode: dedicated lcd-interface. the external nand flash is accessible in both modes. the block diagram figure 9 gives a high level overview of the modules in the chip that are involved in the pin interface multiplexing between the ebi, nand flash controller, mpmc, and ram-based lcd interface. nand flash related pin multiplexing mnand_rybn0 nand_rybn0 mci_dat_4 nand_rybn0 ? nand flash controller read/not busy signal 0. mci_dat_4 ? mci card data input/output line 4. mnand_rybn1 nand_rybn1 mci_dat_5 nand_rybn1 ? nand flash controller read/not busy signal 1. mci_dat_5 ? mci card data input/output line 5. mnand_rybn2 nand_rybn2 mci_dat_6 nand_rybn2 ? nand flash controller read/not busy signal 2. mci_dat_6 ? mci card data input/output line 6. mnand_rybn3 nand_rybn3 mci_dat_7 nand_rybn3 ? nand flash controller read/not busy signal 3. mci_dat_7 ? mci card data input/output line 7. audio related pin multiplexing mi2stx_data0 i2stx_data0 pcm_da i2stx_data0 ? i2s interface 0 transmit data signal. pcm_da ? pcm serial data line a. mi2stx_bck0 i2stx_bck0 pcm_fsc i2stx_bck0 ? i2s interface 0 transmit bitclock signal. pcm_fsc ? pcm frame synchronization signal. mi2stx_ws0 i2stx_ws0 pcm_dclk i2stx_ws0 ? i2s interface 0 transmit word select signal. pcm_dclk ? pcm data clock output. mi2stx_clk0 i2stx_clk0 pcm_db i2stx_clk0 ? i2s interface 0 transmit clock signal. pcm_db ? pcm serial data line b. uart related pin multiplexing muart_cts_n uart_cts_n spi_cs_out1 uart_cts_n ? uart modem control clear-to-send signal. spi_cs_out1 ? spi chip select out for slave 1 (used in master mode). muart_rts_n uart_rts_n spi_cs_out2 uart_rts_n ? uart modem control request-to-send signal. spi_cs_out2 ? spi chip select out for slave 2 (used in master mode). table 11. pin descriptions of multiplexed pins pin name default signal alternate signal description
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 38 of 88 nxp semiconductors lpc3152/3154 figure 9 only shows the signals that are involv ed in pad-muxing, so not all interface signals are visible. the ebi unit between the nand flash interface and the mpmc contains an arbiter that determines which interface is muxed to the outside world. both nand flash and sdram/sram initiate a request to the ebi uni t. this request is granted using round-robin arbitration (see section 6.6 ). 6.28.3 supply domains as is shown in figure 9 the ebi (nand flash/mpmc-control/data) is connected to a different supply domain than the lcd interf ace. the ebi control and address signals are muxed with the lcd interface signals and are part of supply domain sup8. the sdram/sram data lines are shared with the na nd flash through the ebi and are part of supply domain sup4. therefore the following rules apply for connecting memories: 1. sdram and bus-based lcd or sram: this is the mpmc mode. the supply voltage for sdram/sram/bus-based lcd and nand flash must be the same.the dedicated lcd interface is not available in this mpmc mode. fig 9. diagram of lcd and mpmc multiplexing nand_rybn[0:3] nand_ncs_[0:3] nand flash interface control control control data lcd_db_[1:0], control control control (ale, cle) ebi_a_0_ale ebi_a_1_cle ebi 2 16 data 2 6 data 16 address ebi_a_[15:2] 14 14 data lcd_db_[15:2] 14 6 ebi_ncas_blout_0 ebi_nras_blout_1 ebi_dqm_0_noe lcd_csb/ebi_nstcs_0 lcd_db_1/ebi_nstcs_1 lcd_db_0/ebi_clkout lcd_e_rd/ebi_cke lcd_rs/ebi_ndycs lcd_rw_wr/ebi_dqm_1 lcd_db_[15:2] (lcd mode)/ ebi_a_[15:2] (mpmc mode) ebi_d_[15:0] 16 data 16 address mpmc lcd address ebi_a_[1:0] 2 6 3 syscreg_mux_lcd_ebi_sel register (i/o multplexing) mpmc mode lcd mode lpc31xx 002aae157 sup4 sup8 0 1 0 1
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 39 of 88 nxp semiconductors lpc3152/3154 2. dedicated lcd interface only : this is the lcd mode. th e nand flash supply voltage (sup4) can be different from the lcd supply voltage (sup8). 6.29 timer module the lpc3152/3154 contains four fully indep endent timer modules, which can be used to generate interrupts after a pre-set time interval has elapsed. this module has the following features: ? each timer is a 32 bit wide down-counter with selectable pre-scale. the pre-scaler allows using either the module clock directly or the clock divided by 16 or 256. ? two modes of operation: ? free-running timer: the timer generates an interrupt when the counter reaches zero. the timer wraps around to 0xffff ffff and continues counting down. ? periodic timer: the timer generates an in terrupt when the counter reaches zero. it reloads the value from a load register an d continues counting down from that value. an interrupt will be generated every ti me the counter reaches zero. this effectively gives a repeated interrupt at a regular interval. ? at any time the current timer value can be read. ? at any time the value in the load register may be re-written, causing the timer to restart. 6.30 pulse width modul ation (pwm) module this pwm can be used to generate a pulse width modulated or a pulse density modulated signal. with an external low pass filter, the module can be used to generate a low frequent analog signal. a typical use of the output of the module is to control the backlight of an lcd display. this module has the following features: ? supports pulse width modulation (pwm) with software controlled duty cycle. ? supports pulse density modulation (pdm) with software controlled pulse density. 6.31 system control registers the system control registers (syscreg) module provides a register interface for some of the high-level settings in the system such as multiplexers and mode settings. this is an auxiliary module included in this over view for the sake of completeness. 6.32 audio subsystem (adss) the audio subsystem consists of the following blocks: ? i 2 s interfaces on the digital die (see section 6.32.1 ): ? i 2 s0 digital audio input/output (i2srx_0/i2stx_0) ? i 2 s1 (i2srx_1/i2stx_1) interface to the audio analog block (i 2 s1 signals not pinned out) ? edge detector
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 40 of 88 nxp semiconductors lpc3152/3154 ? audio codec on the analog die (see section 7.2 ): ? class ab amplifier ? stereo analog-to-digital converter (sadc) ? analog inputs/outputs ? analog volume control (avc) ? stereo digital-to-analog converter (sdac) ? i 2 s and i 2 c interfaces on the analog die for communication with the digital die. 6.32.1 i 2 s0/1 digital audio input/output the i 2 s0/1 audio module provides a 3-wire digita l audio interface that complies with the i 2 s standard. remark: in the lpc3152/3154, the i 2 s0 interface is pinned out. the i 2 s1 interface is internally connected to the analog die. fig 10. audio paths block diagram decimator interpolator class ab lpc3152/3154 hp_fcl hp_fcr hp_outr hp_outl i 2 s1 i 2 c1 i 2 c i 2 s i 2 s0 hp_outc dmux mux_r1 mux_r0 mux_l0 sdac sdac avc i2stx_1 signals i2srx_1 signals i2stx_data0 i2stx_bck0 i2stx_ws0 i2stx_clk0 adc_mic adc_vinl adc_tinl i2srx_data0 i2srx_bck0 i2srx_ws0 mux_l1 adc_vinr adc_tinr stereo adc sadc analog die/audio codec 002aae558 apb
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 41 of 88 nxp semiconductors lpc3152/3154 the i 2 s0/1 module has the following features: ? receive input supports master mode and slave mode. ? transmit output supports master mode. ? supports lsb justified words of 16, 18, 20 and 24 bits. ? supports a configurable number of bit clock periods per word select period (up to 128 bit clock periods). ? supports dma transfers. ? transmit fifo or receive fifo of 4 stereo samples. ? supports single 16-bit transfers to/from the left or right fifo. ? supports single 24-bit transfers to/from the left or right fifo. ? supports 32-bit interleaved transfers, with the lower 16 bits representing the left audio sample and the higher 16 bits representing the right audio sample. ? supports two 16-bit samples audio samples combined in a 32-bit word (2 left or 2 right samples) to reduce bus load. ? provides maskable interrupts for audio status. (fifo underrun/overrun/full/half_full/not empty for left and right channel separately). 7. functional description of the analog die blocks 7.1 analog die the analog die part of the lpc3152/3154 co ntains the audio codec, the real-time clock (rtc), the power supply unit (psu), the li-ion charger, and the usb charge pump.
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 42 of 88 nxp semiconductors lpc3152/3154 7.2 audio codec 7.2.1 stereo digital-to-analog converter (sdac) the stereo digital-to-analog converter conver ts a digital audio signal into an analog audio signal. the output of this module is connected to the input of the class ab headphone amplifier. this module has the following features: ? stereo digital-to-analog converter wit h support for 24-bit audio samples. ? supports sample rates from 8 khz up to 96 khz. ? filter implementations have a 24-bi t data path with 16-bit coefficients. ? full fir filter implementation for all of the up-sampling filters. fig 11. block diagram of the analog die from usb_vbus psu_vbat1, psu_vbat2, psu_vin1 psu_vbat psu_vbus charge_vbus psu_vout1 psu_stop psu_play psu_vout2 psu_vout3 psu_lx1, psu_lx2 to usb device charge_vbat psu audio codec i 2 c usb charge pump real-time clock li-ion charger i 2 s adc_vinr, adc_vinl, adc_mic, adc_ tinr, adc_tinl adc_vrefp, adc_vrefn adc_vref analog input analog output hp_outr, hp_outl, hp_outc hp_vref, hp_fcr, hp_fcl dac_vrefp, dac_vrefn to i 2 c1 (digital die) to i 2 s1 (digital die) charge_cc_ref charge_vss charge_vntc, charge_bat_sense uos_vbus uos_cx1, uos_cx2 uos_vbat fslow_in fslow_out rtc_int rtc_clk32 rtc_backup rtc_vdd36 lpc3152/3154 to supply pins li-ion battery 002aae754 analog die
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 43 of 88 nxp semiconductors lpc3152/3154 ? controlled power down sequence comprising a raised cosine mute function followed by a dc ramp down to zero to avoid audible plops or clicks. ? digital db-linear volume co ntrol in 0.25 db steps. ? digital de-emphasis for 32 khz, 44.1 khz, 48 khz, and 96 khz. ? selection for the up-sampling filter characteristics (sharp/slow roll-off). ? support for 2fs and 8fs input signals. ? soft mute with a raised cosine function. 7.2.2 class ab headphone amplifier the class ab headphone amplifier amplifies an analog input signal to levels appropriate for a headphone output. its input can be chosen from the stereo digital-to-analog converter (sadc) or from the analog bypass from the tuner input (through the analog volume control (avc) block). the class ab amplifier offers a solution in cases where high output levels are required or when the headp hone wire is also used as an antenna for tuner reception. this module has the following features: ? stereo headphone amplifier. ? three outputs: left, right, and a common signal ground output. ? common signal ground output enables dc co upling of headphone without electrolytic capacitors. ? 16 and higher output drive capability. ? individual power down modes for each output. ? programmable short-circuit current protection for each amplifier. ? additional input with analog volume control (avc) directly connected to the tuner input pins. 7.2.3 stereo analog-to-digital converter (sadc) for audio the stereo adc can convert analog audio input signals into digital audio signals as shown in figure 12 . the module has three input signals: stereo line-in (adc_vinl/adc_vinr), stereo tuner-in (a dc_tinl/adc_tinr), and mono microphone in (adc_mic). these signals can be pre- processed by a low-noise amplifier (lna, microphone input only), a programmable gain amplifier (pga), and a single-to-differential converter (sdc) before they arrive at the input of the actual sadc.
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 44 of 88 nxp semiconductors lpc3152/3154 this module has the following features: ? three input options: line-in (stereo), tuner-in (stereo), microphone-in (mono). ? low-noise amplifier (lna) with a fixed 30 db gain for the microphone input. ? programmable gain amplifier (pga). gain can be set in steps of 3 db up to 24 db. ? single-to-differentia l converter (sdc). ? sadc (switched cap). ? supported audio sample frequencies are 8 khz to 55 khz. ? oversampling rate 128 times the sample frequency. ? high dynamic range. ? digital db-linear volume control in 0.5 db steps. ? dc blocking filter (optional). ? soft start-up. ? mute and overflow detection. 7.3 li-ion charger the built-in charger allows a li-ion battery to be charged from the power supplied by a usb connection or by an ac adapter. this module has the following features: ? monitors for battery voltage, charge curren t, battery temperature feedback (ntc), and chip temperature (programmable temperature limits). ? maximum charge current 250 ma. fig 12. stereo adc for audio lna pga pga pga sdc sdc sdc lpc3152/3154 mux_r1 mux_r0 mux_l0 adc_vinr adc_tinr adc_mic adc_vinl adc_tinl mux_l1 sadc right out left out 002aae559 analog die/stereo adc
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 45 of 88 nxp semiconductors lpc3152/3154 ? the nominal charge current is programmed with an external program-resistor. this allows the charge current to be adapted to the usb enumeration. ? uses a widespread method to charge a li-ion battery with the following stages: ? trickle charging with a small current for an (almost) empty battery. ? fast charging in constant current mode (cc mode) to the maximum battery voltage of 4.2 v 1%. ? switch from cc mode to constant voltage charging (cv mode) keeping the battery voltage at 4.2 v and monitoring the current for ending the charge process. ? short circuit resistant. ? charger state can be observed through a register. 7.4 usb charge pump (host mode) the usb charge pump uses the li-ion batter y to provide a low-po wer usb vbus signal for the usb controller in host mode. 7.5 power supply unit (psu) the integrated psu allows the system to run directly from the battery voltage or the usb power supply voltage usb_vbu s. it converts the battery voltage or the usb_vbus voltage into the supply voltages required for both the digital and analog blocks in the rest of the system.
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 46 of 88 nxp semiconductors lpc3152/3154 this module has the following features: ? takes power from the li-ion battery or the usb power supply. ? outputs in li-ion battery mode: ? psu_vout1, 2.4 v to 3.2 v (software programmable in 8 levels), 100 ma (analog power supply and i/o). ? psu_vout2, 0.9 v to 1.4 v (software programmable in 8 levels), 100 ma (digital power supply). ? psu_vout3, 1.4 v or 1.8 v (software selectable), 50 ma (digital power supply). ? psu_vout1 and psu_vout2 are generated by two inductive dc-to-dc buck converters with internal power switches. ? psu_vout3 is generated by an ldo from psu_vout1. ? outputs in usb power supply mode: ? psu_vout1, 3.3 v, 80 ma. ? psu_vout2, 1.2 v, 80 ma. ? psu_vout3, 1.4 v or 1.8 v (software selectable), 50 ma. ? psu_vout1 is generated by an ldo from the 5 v usb power supply. ? psu_vout2 and psu_vout3 are generated by an ldo from psu_vout1. fig 13. lpc3152/3154 supply voltages of the analog and digital die psu_vout2 psu_vout1 psu_vout3 usb_vbus psu psu_vbus psu_vbat psu_vbat1 rtc_backup rtc_vdd36 psu_vbat2 uos_vbat uos_vbus charge_vbus li-ion charger usb charge pump lpc3152/3154 lpc3152/3154 002aae465 sup3 sup5 sup4/8 3.3 v mode sup4/8 1.8 v mode sup1 sup3 sup2 to usb device charge_vbat charge_cc_ref charge_vss li-ion battery rtc analog die digital die
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 47 of 88 nxp semiconductors lpc3152/3154 ? provides ?supply_ok? detection conn ected to the system reset signal. 7.6 real-time clock (rtc) the real-time clock module keeps track of the actual date and time, also when the system is switched off. advanced digital rights management (drm) schemes require a secure and accurate real-time clock for manag ing rights such as time-limited playback rights. this module has the following features: ? normal power supply directly from li-ion battery (psu is by-passed). ? backup power supply from (external) capacitor. ? automatic switching between normal power supply and backup power supply. ? signals power loss to indicate invalid real time clock readings. ? runs on a 32 khz oscillator. ? ultra-low power consumption. ? the clock is implemented as a 32-bit counter at the rate of 1 hz (derived from the 32 khz clock). ? alarm timer that can generate an interrupt. this interrupt is available both as an internal signal as well as a signal on an external pin. ? the external interrupt (rtc_int) can be us ed to switch on the system by switching on the psu through the psu_play pin. ? the internal interrupt signal can be used to wake-up the system from suspend mode through the event router. ? dedicated permanent supply domain.
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 48 of 88 nxp semiconductors lpc3152/3154 8. limiting values [1] the following applies to the limiting values: a) this product includes circuitry specif ically designed for the protection of its in ternal devices from the damaging effects of excessive static charge. nonetheless, it is sugges ted that conventional precautions be tak en to avoid applying greater than the rated maximum. b) parameters are valid over operating te mperature range unless otherwise specifi ed. all voltages are with respect to v ss unless otherwise noted. [2] dependent on package type. [3] human body model: equivalent to dischar ging a 100 pf capacitor through a 1.5 k series resistor. 9. static characteristics 9.1 digital die table 12. limiting values in accordance with the absolute ma ximum rating system (iec 60134). [1] symbol parameter conditions min typ max unit all digital i/o pins v i input voltage ? 0.5 - +3.6 v v o output voltage ? 0.5 - +3.6 v i o output current vdde_ioc = 3.3 v - 4 - ma temperature values t j junction temperature ? 40 25 125 c t stg storage temperature [2] ? 65 - +150 c t amb ambient temperature ? 40 +25 +85 c electrostatic handling v esd electrostatic discharge voltage human body model [3] ? 500 - +500 v machine model ? 100 - +100 v charged device model -500- v table 13: static characteristics t amb = ? 40 c to +85 c unless otherwise specified. symbol parameter conditions min typ max unit supply pins v dd(io) input/output supply voltage nand flash controller pads (sup4) and lcd interface (sup8); 1.8 v mode 1.65 1.8 1.95 v nand flash controller pads (sup4) and lcd interface (sup8); 3.3 v mode 2.5 3.3 3.6 v other peripherals (sup 3) 2.7 3.3 3.6 v v dd(core) core supply voltage (sup1) 1.1 1.2 1.3 v
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 49 of 88 nxp semiconductors lpc3152/3154 v dd(osc_pll) oscillator and pll supply voltage on pin vdda12; for 12 mhz oscillator (sup1) 1.0 1.2 1.3 v v dd(adc) adc supply voltage on pin adc10b_vdda33; for 10-bit adc (sup 3) 2.7 3.3 3.6 v v prog(pf) polyfuse programming voltage on pin vpp; write 3.0 3.3 3.6 v on pin vpp; read 1.1 - 1.3 v v bus bus supply voltage on pin usb_vbus (sup5) -5.0- v v dda(usb)(3v3) usb analog supply voltage (3.3 v) on pin usb_vdda33 (sup 3) 3.0 3.3 3.6 v on pin usb_vdda33_drv (sup 3); driver 2.7 3.3 3.6 v v dda(pll)(1v2) pll analog supply voltage (1.2 v) on pin usb_vdda12_pll (sup1) 1.1 1.2 1.3 v input pins and i/o pins configured as input v i input voltage 0 - vdde_ioc v v ih high-level input voltage sup3; sup4; sup8 0.7vdde_iox (x = a, b, c) -- v v il low-level input voltage sup3; sup4; sup8 - - 0.3vdde_iox (x = a, b, c) v v hys hysteresis voltage sup4; sup8; v 1.8 v mode 400 - 600 mv 3.3 v mode 550 - 850 mv sup3 0.1vdde_ioc - - v i il low-level input current v i = 0 v; no pull-up - - a i ih high-level input current v i = v dd(io) ; no pull-down - - a i latch i/o latch-up current ? (1.5v dd(io) ) < v i < (1.5v dd(io) ) [1] - - 100 ma i pu pull-up current inputs with pull-up; v i = 0; sup4; sup8; 1.8 v mode [1] 65 a sup4; sup8; 3.3 v mode [1] 50 a sup3 50 a i pd pull-down current inputs with pull-down; v i = v dd ; sup4; sup8; 1.8 v mode [1] 75 a table 13: static characteristics t amb = ? 40 c to +85 c unless otherwise specified. symbol parameter conditions min typ max unit
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 50 of 88 nxp semiconductors lpc3152/3154 sup4; sup8; 3.3 v mode [1] 50 a sup3 [1] 50 a c i input capacitance excluding bonding pad capacitance - - pf output pins and i/o pins configured as output v o output voltage - v dd(io) v v oh high-level output voltage sup4; sup8; i oh = 6 ma: 1.8 v mode v 3.3 v mode v dd(io) ? 0.26 v sup3; i oh = 6 ma v dd(io) ? 0.26 - - v sup3; i oh = 30 ma v dd(io) ? 0.38 - - v v ol low-level output voltage sup4; sup8 outputs; i ol = 4 ma 1.8 v mode v 3.3 v mode [1] 0.65 v sup3; i ol = 4 ma - - v i oh high-level output current v dd = vdde_iox (x = a, b, c); v oh = v dd ? 0.4 v - - ma v dd = vdde_iox (x = a, b, c); v oh = v dd ? 0.4 v - - ma i ol low-level output current v dd = vdde_iox (x = a, b, c); v ol = 0.4 v - - ma v dd = vdde_iox (x = a, b, c); v ol = 0.4 v - - ma i oz off-state output current v o = 0 v; v o =v dd ; no pull-up/down - - 0.064 a i ohs high-level short-circuit output current v dd = vdde_iox (x = a, b, c); v oh = 0 v - - ma v dd = vdde_iox (x = a, b, c); v oh = 0 v - - ma i ols low-level short-circuit output current v dd = vdde_iox (x = a, b, c); v ol = v dd - - ma v dd = vdde_iox (x = a, b, c); v ol = v dd - - ma z o output impedance v dd = vdde_iox (x = a, b, c) 1.8 v mode [1] 45 3.3 v mode [1] 35 table 13: static characteristics t amb = ? 40 c to +85 c unless otherwise specified. symbol parameter conditions min typ max unit
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 51 of 88 nxp semiconductors lpc3152/3154 [1] the parameter values specified are simulated values. [1] on pin adc10b_gnda. [2] conditions: v ssa = 0 v on pin adc10b_gnda, v dd(adc) =3.3v. [3] the adc is monotonic, there are no missing codes. [4] the differential linearity error (e d ) is the difference between the actual step width and the ideal step width. see figure 14 . i 2 c0-bus pins i oz off-state output current v o = 0 v; v o =v dd ; no pull-up/down - - 7.25 a v ih high-level input voltage [1] 0.7vdde_ioc - - v v il low-level input voltage [1] - - 0.3vdde_ioc v v hys hysteresis voltage 0.1vdde_ioc - - v v ol low-level output voltage i ols = 3 ma - - 0.298 v i li input leakage current vdde voltage domain; t amb = 25 c [1] - 1.7 a vdd voltage domain; t amb = 25 c [1] - 0.01 a usb v i(cm) common-mode input voltage high-speed mode ? 50 200 500 mv full-speed/low-speed mode 800 - 2500 mv chirp mode ? 50 - 600 mv v i(dif) differential input voltage 100 400 1100 mv table 13: static characteristics t amb = ? 40 c to +85 c unless otherwise specified. symbol parameter conditions min typ max unit table 14. static characteristics of the 10 bit adc v dd(adc) = 2.7 v to 3.6 v; t amb = ? 40 c to +85 c unless otherwise specified; adc frequency . symbol parameter conditions min typ max unit v ia analog input voltage 0 [1] -v dd(adc) v c ia analog input capacitance - - pf n res(adc) adc resolution 2 - 10 bit e d differential linearity error [2] [3] [4] -- 1lsb e l(adj) integral non-linearity [2] [5] -- 1lsb e o offset error [2] [6] - - lsb e g gain error [2] [7] --< t b d >% e t absolute error [2] [8] - - lsb v err(o) offset error voltage ? 20 - +20 mv v err(fs) full-scale error voltage - mv r vsi voltage source interface resistance --k
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 52 of 88 nxp semiconductors lpc3152/3154 [5] the integral non-linearity (e l(adj) ) is the peak difference between the center of the st eps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. see figure 14 . [6] the offset error (e o ) is the absolute difference between the straight line which fits the actual cu rve and the straight line which fits the ideal curve. see figure 14 . [7] the gain error (e g ) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. see figure 14 . [8] the absolute error (e t ) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated adc and the ideal transfer curve. see figure 14 . [9] see figure 15 .
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 53 of 88 nxp semiconductors lpc3152/3154 (1) example of an actual transfer curve. (2) the ideal transfer curve. (3) differential linearity error (e d ). (4) integral non-linearity (e l(adj) ). (5) center of a step of the actual transfer curve. fig 14. adc characteristics 002aae752 1023 1022 1021 1020 1019 (2) (1) 1024 1018 1019 1020 1021 1022 1023 7 123456 7 6 5 4 3 2 1 0 1018 (5) (4) (3) 1 lsb (ideal) code out v dd(adc) ? v ssa 1024 offset error e o gain error e g offset error e o v ia (lsb ideal ) 1 lsb =
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 54 of 88 nxp semiconductors lpc3152/3154 9.2 analog die 9.2.1 psu fig 15. suggested 10-bit adc interface lpc3152/3154 adc sample ad10b_gpa[0:2] tbd k tbd pf tbd pf r vsi v ssa v ext 002aae563 table 15. static characteristics of the analog die supply pins t amb = ? 40 c to +85 c unless otherwise specified. symbol parameter conditions min typ max unit v dd(io) input/output supply voltage peripheral supply of the analog die; sup3 2.7 3.3 3.6 v v dd(core) core supply voltage core supply of the analog die; sup2 1.3 1.4 1.95 v table 16: static characteristics of the psu t amb = ? 40 c to +85 c unless otherwise specified. symbol parameter conditions min typ max unit v i(vbus) v bus input voltage on pin psu_vbus 4.0 5 5.5 v v bat battery supply voltage on pin psu_vbat 2.7 3.7 4.2 v output psu_vout1 v o output voltage generated from psu_vbat (programmable in 8 levels) 2.4 2.8 3.2 v generated from psu_vbus 3.1 3.3 3.5 v v o output voltage deviation output voltage generated from psu_vbat [1] ? 100 - +100 mv i o output current on pin psu_vout1 --8 0m a i l(ldo)(max) maximum ldo load current on ldo1 200 250 - ma
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 55 of 88 nxp semiconductors lpc3152/3154 [1] deviation of output voltage on pin psu_voutn from its nominal, programmed value. output psu_vout2 v o output voltage generated from psu_vbat (programmable in 8 levels) 0.9 1.04 1.4 v generated from psu_vbus (ldo1 on) 1.15 1.2 1.25 v v o output voltage deviation output voltage generated from psu_vbat [1] ? 50 - +50 mv i o output current on pin psu_vout2 --8 0m a i l(ldo)(max) maximum ldo load current on ldo2 80 100 - ma output psu_vout3 v o output voltage generated from either psu_vbat or psu_vbus (programmable in 2 levels) -1 . 41 . 8v on ldo3 of v o = 1.4 v (default) 1.35 1.4 1.45 v on ldo3 of v o = 1.8 v (default) 1.75 1.8 1.85 v i o output current on pin psu_vout3 -5 0 m a i l(ldo)(max) maximum ldo load current on ldo3 50 - ma dc-to-dc converter (dcdc) dc-to-dc converter efficiency -85-% f clk clock frequency - 12 - mhz f osc oscillator frequency 8 10 12 mhz f sw switching frequency - 1 - mhz table 16: static characteristics of the psu ?continued t amb = ? 40 c to +85 c unless otherwise specified. symbol parameter conditions min typ max unit
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 56 of 88 nxp semiconductors lpc3152/3154 9.2.1.1 psu_vout1 efficiency table 17: static characteristics of the analog input t amb = ? 40 c to +85 c unless otherwise specified. symbol parameter conditions min typ max unit i dda(adc)(3v3) adc analog supply current (3.3 v) per mono adc; normal operation -2.2-ma i dda(adc)(1v8) adc analog supply current (1.8 v) per mono adc; normal operation --20 a i ref(neg) negative reference current per mono adc; normal operation -20- a i ref(pos) positive reference current per mono adc; normal operation -2 0- a i dda(sdc) sdc analog supply current - 0.4 - ma i dda(pga) pga analog supply current - 430 - a g pga pga gain - -1.94 - db i dda(bias) bias analog supply current n = 13 for all modules on; normal operation -190+n 10 - a i dda(lna) lna analog supply current - 0.85 1.2 ma g lna lna gain in a bandwidth between 300 hz and 5 khz. 28 30 32 db r ref reference resistance headphone and dac - 11.25 k r com common resistance headphone - 11.25 k g gain step size 3 db 0 - 24 db sup3 = 2.86 v. sup1: v dd = 1.071 v, i dd = 0 ma. sup2: v dd = 1.396 v, i dd = 0 ma. psu_vout1 = 2.86 v. fig 16. efficiency of psu_vout1 i dd (ma) 0 30 20 10 002aae466 60 40 80 100 (%) 20
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 57 of 88 nxp semiconductors lpc3152/3154 9.2.1.2 psu_vout2 efficiency table 18. efficiency of output on psu_vout1 (psu_vout1 programmed to 2.86 v) i bat / ma v bat / v i dd / ma v dd / v efficiency / % on pin psu_vbat (sup3) (sup4) 2 3.602 1 2.8676 39.80566352 2.8 3.6016 2 2.864 56.80015231 3.598 - 3 2.8605 66.22816876 4.396 3.601 4 2.8569 72.18953182 5.195 3.6006 5 2.8533 76.27057345 5.994 3.6003 6 2.8498 79.23374865 6.793 3.5999 7 2.8462 81.47256753 7.59 3.5995 8 2.8426 83.23802841 8.388 3.5992 9 2.83991 84.63671469 9.231 3.5988 10 2.8542 85.9167695 13.32 3.597 15 2.8549 89.37941277 17.368 3.595 20 2.837 90.87420537 25.59 3.591 30 2.8198 92.056375145 sup1 = 1.07 v. sup2: v dd = 1.398 v, i dd = 0 ma. sup3: v dd = 2.912 v, i dd = 0 ma. psu_vout2 = 1.07 v. fig 17. efficiency psu_vout2 i dd (ma) 0 30 20 10 002aae467 60 40 80 100 (%) 20
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 58 of 88 nxp semiconductors lpc3152/3154 table 19. efficiency of output on psu_vout2 (psu_vout2 programmed to 1.07 v) i bat / ma v bat / v i dd / ma v dd / v efficiency / % on pin psu_vbat for supply domain sup1 1.002 3.602 1 1.072 29.70184007 1.357 3.6022 2 1.069 43.7381119 1.71 3.6021 3 1.068 52.0164407 2.063 3.6019 4 1.067 57.43723586 2.415 3.6018 5 1.0664 61.29900313 2.77 3.6016 6 1.0655 64.08102616 3.122 3.6015 7 1.0647 66.28404084 3.472 3.6013 8 1.0638 68.06297931 3.822 3.6011 9 1.0628 69.49734136 4.172 3.601 10 1.0619 70.68319948 5.7 3.6003 15 1.0218 74.68675856 7.292 3.5997 20 1.0258 78.15913105 10.466 3.5983 30 1.0151 80.86339729
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 59 of 88 nxp semiconductors lpc3152/3154 9.2.2 li-ion charger [1] reversed current spec: for v bat = 3.2 v (no usb and 100 k to ground). table 20: static characterist ics of the li-ion charger symbol parameter conditions min typ max unit v bat battery voltage cs_bits at 0000 - - 4.25 v i load load current due to charger when 5 v is disconnected [1] -3-m a constant-current charge (fast charge) mode i bat battery current r ext = 1.00 k 95 100 105 ma r ext = 400 237.5 250 262.5 ma trickle charge mode v th(trch)bat battery trickle charge threshold voltage battery voltage rising -2 . 8-v battery voltage falling -2 . 7-v constant-voltage charge mode v th(cvch)bat battery constant-voltage charge threshold voltage after compensation using cs_bits 4.158 4.2 4.242 v recharge mode v th(rech)bat battery recharge threshold voltage - 4.05 - v
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 60 of 88 nxp semiconductors lpc3152/3154 10. dynamic characteristics 10.1 digital die 10.1.1 lcd controller 10.1.1.1 intel 8080 mode [1] timing is determined by the lcd interface control register fields: invert_cs = 1; mi = 0; ps = 0; invert_e_rd = 0. see the lpc315x user manual . table 21. dynamic characteristics: lcd controller in intel 8080 mode c l =25pf, t amb = ? 40 c to +85 c, unless otherwise specified; v dd(io) = 1.8 v and 3.3 v (sup8). symbol parameter conditions min typ max unit t su(a) address set-up time - 1 lcdclk - ns t h(a) address hold time - 2 lcdclk - ns t cy(a) access cycle time [1] -5 lcdclk - ns t w(en)w write enable pulse width [1] -2 lcdclk - ns t w(en)r read enable pulse width [1] -2 lcdclk - ns t r rise time 2 - 5 ns t f fall time 2 - 5 ns t su(d) data input set-up time - - ns t h(d) data input hold time - - ns t d(qv) data output valid delay time - ? 1 lcdclk - ns t dis(q) data output disable time - 2 lcdclk - ns fig 18. lcd timing (intel 8080 mode) 002aae207 mlcd_rs mlcd_csb mlcd_rw_wr, mlcd_e_rd mlcd_db[15:0] (16 bit mode), mlcd_db[15:8] (8 bit mode), mlcd_db[15:12] (4 bit mode) mlcd_db[15:0] (16 bit mode), mlcd_db[15:8] (8 bit mode), mlcd_db[15:12] (4 bit mode) t h(a) t su(a) t w(en)r and t w(en)w t d(qv) t dis(q) t su(d) t h(d) t f t r t cy(a) read access write access
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 61 of 88 nxp semiconductors lpc3152/3154 10.1.1.2 motorola 6800 mode [1] timing is derived from the lcd interface control register fields: invert_cs = 1; mi = 1; ps = 0; invert_e_rd = 0. see the lpc315x user manual . table 22. dynamic characteristics: lc d controller in motorola 6800 mode c l =25pf, t amb = ? 40 c to +85 c, unless otherwise specified; v dd(io) = 1.8 v and 3.3 v (sup8). symbol parameter conditions min typ max unit t su(a) address set-up time - 1 lcdclk - ns t h(a) address hold time - 2 lcdclk - ns t cy(a) access cycle time [1] -5 lcdclk - ns t r rise time 2 - 5 ns t f fall time 2 - 5 ns t su(d) data input set-up time - - ns t h(d) data input hold time - - ns t d(qv) data output valid delay time - ? 1 lcdclk - ns t dis(q) data output disable time - 2 lcdclk - ns t w(en) enable pulse width read cycle - 2 lcdclk - ns write cycle - 2 lcdclk - ns fig 19. lcd timing (motorola 6800 mode) 002aae208 mlcd_csb mlcd_e_rd mlcd_rs, mlcd_rw_wr mlcd_db[15:0] (16 bit mode), mlcd_db[15:8] (8 bit mode), mlcd_db[15:12] (4 bit mode) mlcd_db[15:0] (16 bit mode), mlcd_db[15:8] (8 bit mode), mlcd_db[15:12] (4 bit mode) t su(d) t d(qv) t su(a) t h(a) t h(d) t f t r write access read access t dis(q) t w(en) t cy(a)
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 62 of 88 nxp semiconductors lpc3152/3154 10.1.1.3 serial mode [1] timing is determined by the lcd interface contro l register fields: ps = 1; serial_clk_shift = 3; serial_read_pos = 3. see the lpc315x user manual . table 23. dynamic characteristi cs: lcd controller serial mode c l =25pf, t amb = ? 40 c to +85 c, unless otherwise specified; v dd(io) = 1.8 v and 3.3 v (sup8). symbol parameter conditions min typ max unit t cy(clk) clock cycle time [1] -5 lcdclk - ns t w(clk)h high clock pulse width [1] -3 lcdclk - ns t w(clk)l low clock pulse width [1] -2 lcdclk - ns t r rise time 2 - 5 ns t f fall time 2 - 5 ns t su(a) address set-up time - 3 lcdclk - ns t h(a) address hold time - 2 lcdclk - ns t su(d) data input set-up time - - ns t h(d) data input hold time - - ns t su(s) chip select set-up time - 3 lcdclk - ns t h(s) chip select hold time - 1 lcdclk - ns t d(qv) data output valid delay time - ? 1 lcdclk - ns fig 20. lcd timing (serial mode) 002aae209 mlcd_csb mlcd_rs mlcd_db13 (serial clock) mlcd_db14 (serial data in) mlcd_db15 (serial data out) t su(d) t su(a) t h(a) t su(s) t h(s) t h(d) t d(qv) t dis(q) t f t r t w(clk)l t w(clk)h t cy(clk)
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 63 of 88 nxp semiconductors lpc3152/3154 10.1.2 sram controller [1] refer to the lpc315x user manual for the programming of waitoen and hclk. [2] refer to the lpc315x user manual for the programming of waitrd and hclk. [3] (waitrd ? waitoen + 1) = 3 min at 60 mhz. [4] refer to the lpc315x user manual for the programming of waitwen and hclk. [5] refer to the lpc315x user manual for the programming of waitwr and hclk. [6] (waitwd ? waitwen + 1) = 3 min at 60 mhz. table 24. dynamic characteristics: static external memory interface c l =25pf, t amb = ? 40 c to +85 c, unless otherwise specified; v dd(io) = 1.8 v and 3.3 v (sup8). symbol parameter conditions min typ max unit common to read and write cycles t cslav cs low to address valid time ? 1.8 0 4 ns read cycle parameters t oelav oe low to address valid time [1] -0 ? waitoen hclk - ns t blslav bls low to address valid time [1] -0 ? waitoen hclk - ns t csloel cs low to oe low time - 0 + waitoen hclk - ns t cslblsl cs low to bls low time [1] - 0 + waitoen hclk - ns t oeloeh oe low to oe high time [1] [2] [3] -(waitrd ? waitoen + 1) hclk - ns t blslblsh bls low to bls high time [1] [2] [3] -(waitrd ? waitoen + 1) hclk - ns t su(d) data input set-up time 9 - - ns t h(d) data input hold time - 0 - ns t cshoeh cs high to oe high time 3 0 - ns t cshblsh cs high to bls high time - 0 - ns t oehanv oe high to address invalid time 10 - - ns t blshanv bls high to address invalid time -1 hclk - ns write cycle parameters t csldv cs low to data valid time - - 9 ns t cslwel cs low to we low time [4] -(waitwen+1) hclk - ns t cslblsl cs low to bls low time [4] - waitwen hclk - ns t weldv we low to data valid time [4] -0 ? (waitwen + 1) hclk - ns t welweh we low to we high time [4] [5] [6] -(waitwr ? waitwen + 1) hclk - ns t blslblsh bls low to bls high time [4] [5] -(waitwr ? waitwen + 3) hclk - ns t wehanv we high to address invalid time -1 hclk - ns t wehdnv we high to data invalid time - 1 hclk - ns t blshanv bls high to address invalid time -1 hclk - ns t blshdnv bls high to data invalid time -1 hclk - ns
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 64 of 88 nxp semiconductors lpc3152/3154 fig 21. external memory read access to static memory t cshoeh t cshblsh t oehanv t blshanv t csloel t oeloeh t cslblsl t blslblsh t cslav t oelav t blslav t h(dq) t su(dq) ebi_nstcs_x ebi_dqm_0_noe ebi_ncas_blout_0 ebi_nras_blout_1 ebi_a_[15:0] ebi_d_[15:0] 002aae161
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 65 of 88 nxp semiconductors lpc3152/3154 10.1.3 sdram controller fig 22. external memory write access to static memory t blslblsh t cslav t csldv t wehanv t cslwel t cslblsl t wehdnv t blshdnv t blshanv t welweh t weldv 002aae162 ebi_nstcs_x ebi_ncas_blout_0 ebi_nras_blout_1 ebi_a_[15:0] ebi_d_[15:0] ebi_nwe table 25. dynamic characteristics of sdr sdram memory interface t amb = ? 40 c to +85 c, unless otherwise specified. [1] [2] [3] symbol parameter conditions min typical max unit f oper operating frequency [4] -80 90 mhz t clcl clock cycle time 11.1 - ns t clcx clock low time - 5.55 - ns t chcx clock high time - 5.55 - ns t d(o) output delay time on pin ebi_cke [5] -- 3.6 ns on pins ebi_nras_blout, ebi_ncas_blout, ebi_nwe, ebi_ndycs -- 3.6 ns on pins ebi_dqm_1, ebi_dqm_0_noe -- 5 ns
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 66 of 88 nxp semiconductors lpc3152/3154 [1] parameters are valid over operating tem perature range unless otherwise specified. [2] all values valid for pads set to high slew rate. vdde_ioa = vdde_iob = 1.8 0.15 v. vddi = 1.2 0.1 v. [3] refer to the lpc3152/3154 user manual for the progra mming of mpmcdynamicreadconfig and syscreg_mpmp_delaymodes registers. [4] f oper = 1 / t clcl [5] t d(o) , t h(o) , t d(av) , t h(a) , t d(qv) , t h(q) times are dependent on mpmcdynamicreadconfig register value and syscreg_mpmp_delaymodes register bits 11:6. [6] t su(d) , t h(d) times are dependent on syscreg_mpmp_d elaymodes register bits 5:0. t h(o) output hold time on pin ebi_cke [5] 0.13 - 3.6 ns on pins ebi_nras_blout, ebi_ncas_blout, ebi_nwe, ebi_ndycs ? 0.1 - 3.6 ns on pins ebi_dqm_1, ebi_dqm_0_noe 1.7 - 5 ns t d(av) address valid delay time [5] -- 5 ns t h(a) address hold time [5] ? 0.1 - 5 ns t d(qv) data output valid delay time [5] -- 9 ns t h(q) data output hold time [5] 4- 10 ns t su(d) data input set-up time [6] - - ns t h(d) data input hold time [6] - - ns t qz data output high-impedance time -- dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 67 of 88 nxp semiconductors lpc3152/3154 ebi_cke is high. fig 23. sdram burst read timing ebi_a_[15:2] ebi_dqmx ebi_d_[15:0] ebi_clkout ebi_nras_blout ebi_ncas_blout ebi_nwe ebi_cke ebi_ndycs t h(o) t h(o) t h(a) t su(d) t h(d) read nop nop nop nop nop read bank, column 002aae121 t clcl t chcx t clcx t d(o) t d(o) cas latency = 2 data n data n+1 data n+2 data n+3
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 68 of 88 nxp semiconductors lpc3152/3154 fig 24. sdram bank activate and write timing ebi_cke write bank, row bank, column 002aae123 ebi_a_[15:2] ebi_d_[15:0] ebi_clkout ebi_nras_blout ebi_ncas_blout ebi_nwe ebi_cke ebi_ndycs t clcl t chcx t clcx t h(o) t h(o) t d(o) t d(o) t d(av) t d(qv) t h(a) t h(q) ebi_dqmx t qz active data
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 69 of 88 nxp semiconductors lpc3152/3154 10.2 nand flash memory controller [1] t hclk = 1 / nandflash_nand_clk, see lpc315x user manual . [2] see registers nandtiming1 and nandtiming2 in the lpc315x user manual . [3] each timing parameter can be set from 7 nand_clk cl ock cycles to 1 nand_clk clock cycle. (a programmed zero value is treated as a one). table 26. dynamic characteristics of the nand flash memory controller t amb = ? 40 c to +85 c, unless otherwise specified. symbol parameter typical unit t reh re high hold time [1] [2] [3] t hclk (treh) ns t rp re pulse width [1] [2] [3] t hclk (trp) ns t wh we high hold time [1] [2] [3] t hclk (twh) ns t wp we pulse width [1] [2] [3] t hclk (twp) ns t cls cle set-up time [1] [2] [3] t hclk (tcls) ns t clh cle hold time [1] [2] [3] t hclk (tclh) ns t als ale set-up time [1] [2] [3] t hclk (tals) ns t alh ale hold time [1] [2] [3] t hclk (talh) ns t cs ce set-up time [1] [2] [3] t hclk (tcs) ns t ch ce hold time [1] [2] [3] t hclk (tch) ns fig 25. nand flash controller write and read timing ebi_nwe ebi_a_1_cle ebi_a_0_ale t wp t cs t ch t cls t clh mnand_ncs t wh 002aae353 t als t alh t rp t reh ebi_dqm_0_noe
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 70 of 88 nxp semiconductors lpc3152/3154 10.2.1 crystal oscillator 10.2.2 spi remark: note that the signal names sck, miso , and mosi correspond to signals on pins spi_sck, spi_mosi, and spi_miso in the following spi timing diagrams. table 27: dynamic characteristics: crystal oscillator symbol parameter conditions min typ max unit f osc oscillator frequency 10 12 25 mhz clk clock duty cycle 45 50 55 % c xtal crystal capacitance input; on pin ffast_in -- 2 pf output; on pin ffast_out - - 0.74 pf t startup start-up time - 500 - s p drive drive power 100 - 500 w table 28. dynamic characteristics of spi pins t amb = ? 40 c to +85 c for industrial applications symbol parameter min typ max unit spi master t spicyc spi cycle time 22.2 - - ns t spiclkh spiclk high time 11.09 - 11.14 ns t spiclkl spiclk low time 11.09 - 11.14 ns t spidsu spi data set-up time ns t spidh spi data hold time ns t spiqv spi data output valid time - - 14 ns t spioh spi output data hold time 9.9 - - ns spi slave t spicyc spi cycle time 40 ns t spiclkh spiclk high time 20 ns t spiclkl spiclk low time 20 ns t spidsu spi data set-up time ns t spidh spi data hold time ns t spiqv spi data output valid time 14 ns t spioh spi output data hold time 9.9 - - ns
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 71 of 88 nxp semiconductors lpc3152/3154 fig 26. spi master timing (cpha = 1) fig 27. spi master timing (cpha = 0) sck (cpol = 0) mosi miso 002aad986 t spiclk t spiclkh t spiclkl t spidsu t spidh t spisedv data valid data valid t spioh sck (cpol = 1) data valid data valid sck (cpol = 0) mosi miso 002aad987 t spiclk t spiclkh t spiclkl t spidsu t spidh data valid data valid t spioh sck (cpol = 1) data valid data valid t spisedv
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 72 of 88 nxp semiconductors lpc3152/3154 10.2.2.1 texas in struments synchronous ser ial mode (ssp mode) [1] parameters are valid over operating tem perature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are at room temperature (25 c), nominal supply voltages. remark: note that the signal names sck, miso , and mosi correspond to signals on pins spi_sck, spi_mosi, and spi_miso in the following spi timing diagram. fig 28. spi slave timing (cpha = 1) fig 29. spi slave timing (cpha = 0) sck (cpol = 0) mosi miso 002aad988 t spiclk t spiclkh t spiclkl t spidsu t spidh t spisedv data valid data valid t spioh sck (cpol = 1) data valid data valid sck (cpol = 0) mosi miso 002aad989 t spiclk t spiclkh t spiclkl t spidsu t spidh t spisedv data valid data valid t spioh sck (cpol = 1) data valid data valid table 29. dynamic ch aracteristic: spi in terface (ssp mode) t amb = ? 40 c to +85 c; v dd(io) (sup3) over specified ranges. [1] symbol parameter conditions min typ [2] max unit t su(spi_miso) spi_miso set-up time t amb = 25 c; measured in spi master mode; see figure 30 -1 1-n s
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 73 of 88 nxp semiconductors lpc3152/3154 fig 30. miso line set-up time in ssp master mode t su(spi_miso) sck shifting edges mosi miso 002aad326 sampling edges
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 74 of 88 nxp semiconductors lpc3152/3154 10.2.3 i 2 s-interface [1] x = 0 or 1. table 30. dynamic characteristics: i 2 s-interface pins t amb = ? 40 c to +85 c for industrial applications symbol parameter conditions min typ max unit common to input and output t cy(clk) clock cycle time ns t f fall time 3.5 ns t r rise time 3.5 ns output t wh pulse width high ns t wl pulse width low ns t v(q) data output valid time on pin i2stx_datax [1] ns on pin i2stx_wsx [1] ns input t su(d) data input set-up time on pin i2srx_datax [1] ns on pin i2srx_wsx [1] ns t h(d) data input hold time on pin i2srx_datax [1] ns on pin i2srx_wsx [1] ns fig 31. i 2 s-bus timing (output) 002aad992 i2stx_sck i2stx_sda i2stx_ws t cy t f t r t wh t wl t v(q) t v(q)
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 75 of 88 nxp semiconductors lpc3152/3154 10.2.4 i 2 c-bus [1] parameters are valid over operating tem perature range unless otherwise specified. [2] typical ratings are not guaranteed. the va lues listed are at room temperature (25 c), nominal supply voltages. [3] bus capacitance c b in pf, from 10 pf to 400 pf. fig 32. i 2 s-bus timing (input) 002aad993 i2srx_sck i2srx_sda i2srx_ws t cy t f t r t wh t su(d) t hd) t su(d) t h2 t wl table 31. dynamic characteristic: i 2 c-bus pins t amb = ? 40 c to +85 c. [1] symbol parameter conditions min typ [2] max unit f scl scl clock frequency standard mode 0 100 khz fast mode 0 400 khz t f(o) output fall time v ih to v il 20 + 0.1 c b [3] --ns t r rise time standard mode 1000 ns fast mode 20 + 0.1 c b [3] 300 ns t f fall time standard mode 300 ns fast mode 20 + 0.1 c b [3] 300 ns t buf bus free time between a stop and start condition - t low low period of the scl clock standard mode 4.7 s fast mode 1.3 s t hd;sta hold time (repeated) start condition - t high high period of the scl clock standard mode 4.0 s fast mode 0.6 s t su;dat data set-up time standard mode 250 ns fast mode 100 ns t su;sta set-up time for a repeated start condition - t su;sto set-up time for stop condition standard mode 4.0 s fast mode 0.6 s
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 76 of 88 nxp semiconductors lpc3152/3154 remark: signals sda and scl correspond to pins i2c_sdax and i2c_sclx (x = 0, 1). fig 33. i 2 c-bus pins clock timing p ss p 002aad985 t hd;sta t buf t hd;sta t su;sta t su;dat t f t high t su;sto t r t hd;sta t low sda scl
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 77 of 88 nxp semiconductors lpc3152/3154 10.2.5 usb interface [1] characterized but not implemented as production test. guaranteed by design. 10.2.6 10-bit adc table 32. dynamic characteristi cs: usb pins (high-speed) c l = 50 pf; r pu = 1.5 k on d+ to v dd(io) (sup3), unless otherwise specified. symbol parameter conditions min typ max unit t r rise time 10 % to 90 % - ns t f fall time 10 % to 90 % - ns t frfm differential rise and fall time matching t r /t f --< t b d >% v crs output signal crossover voltage - v t feopt source se0 interval of eop see figure 34 - ns t fdeop source jitter for differential transition to se0 transition see figure 34 - ns t jr1 receiver jitter to next transition - ns t jr2 receiver jitter for paired transitions 10 % to 90 % - ns t eopr1 eop width at receiver must reject as eop; see figure 34 [1] --ns t eopr2 eop width at receiver must accept as eop; see figure 34 [1] --ns fig 34. differential da ta-to-eop transition skew and eop width 002aab561 t period differential data lines crossover point source eop width: t feopt receiver eop width: t eopr1 , t eopr2 crossover point extended differential data to se0/eop skew n t period + t fdeop table 33: dynamic characteristics: 10-bit adc symbol parameter conditions min typ max unit f s sampling frequency 10 bit resolution 400 - - ksamples/s 2 bit resolution - - 1500 ksamples/s t conv conversion time 10 bit resolution - - 11 clock cycles 2 bit resolution 3 - - clock cycles
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 78 of 88 nxp semiconductors lpc3152/3154 10.3 analog die/audio system [1] measured with 20 khz block filter. table 34. dynamic characteristics of class ab amplifier t amb = ? 40 c to +85 c unless otherwise specified. v dd(adc) = 3.3 v on pin adc_vdda33. symbol parameter conditions min typ max unit v o output voltage hp unloaded - 800 - mv(rms) p o output power per channel; rl=16 23.5 mw (thd+n)/s total harmonic distortion plus noise-to-signal ratio at 0 dbfs; f in = 1 khz; rl=16 [1] - ? 60 - db at ? 60 dbfs; f in = 1 khz; rl=16 - ? 40 ? 30 dba s/n signal-to-noise ratio [1] - 100 - dba psrr power supply ripple rejection - 6 - db ct(ch) channel crosstalk rl=16 ; between left channel and right channel - ? 55 - db table 35: dynamic characteristic for analog in t amb = ? 40 c to +85 c unless otherwise specified. symbol parameter conditions min typ max unit b bandwidth - - 20 khz tuner (thd+n)/s total harmonic distortion plus noise-to-signal ratio at 0 dbfs; f in = 1 khz; line input level = 1 v; pga setting +12 db; external resistor of 36 k - ? 83 ? 80 db at 0 dbfs; f in = 1 khz; line input level = 1 v, pga setting 0 db --70- db at ? 60 dbfs; a-weighted; f in = 1 khz; line input level = 1mv, pga setting 0db - ? 34 ? 30 dba s/n signal-to-noise ratio a-weighted; line input = 1 v, pga setting 0 db 90 94 - dba z i input impedance line in (tuner mode) - 12 - k microphone thd total harmonic distortion v i = 20 mv; f in = 1 khz - ? 70 ? 60 db v i = 0.3 mv; f in = 1 khz - ? 90 ? 80 db z i input impedance microphone mode - 5 - k
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 79 of 88 nxp semiconductors lpc3152/3154 11. application information table 36. lcd panel connections tfbga pin # pin name reset function (default) lcd mode parallel serial lcd panel data mapping control function 16 bit 8 bit 4 bit 6800 8080 r8 mlcd_csb/ebi_nstcs_0 lcd_csb - - - lcd_csb lcd_csb lcd_csb p7 mlcd_e_rd/ebi_cke lcd_e_rd - - - lcd_e lcd_rd - r7 mlcd_rs/ebi_ndycs lcd_rs - - - lcd_rs lcd_rs lcd_rs t8 mlcd_rw_wr/ebi_dqm_1 lcd_rw_wr - - - lcd_rw lcd_wr - t7 mlcd_db_0/ebi_clkout lcd_db_0 lcd_db_0 - - - - - p8 mlcd_db_1/ebi_nstcs_1 lcd_db_1 lcd_db_1 - - - - - t6 mlcd_db_2/ebi_a_2 lcd_db_2 lcd_db_2 - - - - - r6 mlcd_db_3/ebi_a_3 lcd_db_3 lcd_db_3 - - - - - u6 mlcd_db_4/ebi_a_4 lcd_db_4 lcd_db_4 - - - - - p6 mlcd_db_5/ebi_a_5 lcd_db_5 lcd_db_5 - - - - - r5 mlcd_db_6/ebi_a_6 lcd_db_6 lcd_db_6 - - - - - t5 mlcd_db_7/ebi_a_7 lcd_db_7 lcd_db_7 - - - - - u5 mlcd_db_8/ebi_a_8 lcd_db_8 lcd_db_8 lcd_db_0 - - - - p5 mlcd_db_9/ebi_a_9 lcd_db_9 lcd_db_9 lcd_db_1 - - - - p4 mlcd_db_10/ebi_a_10 lcd_db_10 lcd_db_10 lcd_db_2 - - - - u4 mlcd_db_11/ebi_a_11 lcd_db_11 lcd_db_11 lcd_db_3 - - - - t4 mlcd_db_12/ebi_a_12 lcd_db_12 lcd_db_12 lcd_db_4 lcd_db_0 - - - u3 mlcd_db_13/ebi_a_13 lcd_db_13 lcd_db_13 lcd_db_5 lcd_db_1 - - ser_clk u2 mlcd_db_14/ebi_a_14 lcd_db_14 lcd_db_14 lcd_db_6 lcd_db_2 - - ser_dat_in r4 mlcd_db_15/ebi_a_15 lcd_db_15 lcd_db_15 lcd_db_7 lcd_db_3 - - ser_dat_out
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 80 of 88 nxp semiconductors lpc3152/3154 12. marking table 37. lpc3152/3154 marking line marking description a lpc3152/3154 basic_type
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 81 of 88 nxp semiconductors lpc3152/3154 13. package outline fig 35. lpc3152/3154 tfbga208 package outline references outline version european projection issue date iec jedec jeita sot930-1 - - - sot930-1 05-12-08 06-01-03 dimensions (mm are the original dimensions) tfbga208: plastic thin fine-pitch ball grid array package; 208 balls; body 12 x 12 x 0.7 mm 0 5 10 mm scale unit mm 0.35 0.25 0.80 0.65 0.45 0.35 12.1 11.9 a 1 a 2 b e 12.1 11.9 d ee 1 v 0.15 10.4 e 2 10.4 0.65 w 0.05 y 0.08 y 1 0.1 a max 1.15 ball a1 index area d e b a b ball a1 index area e 2 e 1 e e ac b v m c w m a b c d e f h k g j l m n p r t u 2 4 6 8 10121416 1 3 5 7 9 11 13 15 17 c y c y 1 x a detail x a 2 a 1
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 82 of 88 nxp semiconductors lpc3152/3154 14. abbreviations table 38: abbreviations acronym description adc analog-to-digital converter adc10b 10 bit analogue to digital converter aes advanced encryption standard avc analog volume control biu bus interface unit cbc cipher block chaining cd compact disk cgu clock generation unit dfu device firmware upgrade dma direct memory access controller drm digital rights management ecc error correction code fir finite input response hp headphones ioconfig input out put configuration rom read only memory irda infrared data association jtag joint test action group isram internal static ram memory jtag joint test action group lcd liquid crystal display ldo low drop voltage output regulator lna low-noise amplifier mmu memory management unit ntc negative temperature coefficient otp one-time programmable memory pcm pulse code modulation pga programmable gain amplifier phy physical layer pll phase locked loop psu power supply unit pwm pulse width modulation rng random number generator sdc sha1 secure hash algorithm 1 sir serial irda spi serial peripheral interface ssi serial synchronous interface syscreg system control registers
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 83 of 88 nxp semiconductors lpc3152/3154 timer timer module uart universal asynchronous receiver transmitter usb 2.0 hs otg universal serial bus 2.0 high-speed on-the-go table 38: abbreviations ?continued acronym description
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 84 of 88 nxp semiconductors lpc3152/3154 15. revision history table 39: revision history document id release date data sheet status change notice supersedes lpc3152_3154 v.0.12 preliminary data sheet - lpc3152_3154_0.11 modifications: ? reset state of jtag pins and gpio0, gpio1, and gpio2 pins updated in ta b l e 4 . ? document template updated. ? digital i/o level for pin clock_out corrected in ta b l e 4 . ? usb hi-speed logo added. ? usb-if testid numbers added in section 6.10 . lpc3152_3154_0.11 preliminary data sheet - -
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 85 of 88 nxp semiconductors lpc3152/3154 16. legal information 16.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 16.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 16.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 86 of 88 nxp semiconductors lpc3152/3154 quick reference data ? the quick reference data is an extract of the product data given in the limiting values and characteristics sections of this document, and as such is not comple te, exhaustive or legally binding. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 16.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 17. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra lpc3152_3154 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. preliminary data sheet rev. 0.12 ? 27 may 2010 87 of 88 continued >> nxp semiconductors lpc3152/3154 18. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 2.1 key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 functional description . . . . . . . . . . . . . . . . . . 16 6.1 arm926ej-s . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.2 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.2.1 analog die memory organization . . . . . . . . . . 17 6.3 jtag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.4 nand flash controller . . . . . . . . . . . . . . . . . . . 18 6.5 multi-port memory controller (mpmc) . . . . . . 20 6.6 external bus interface (ebi) . . . . . . . . . . . . . . 21 6.7 internal rom memory . . . . . . . . . . . . . . . . . . 21 6.8 internal ram memory. . . . . . . . . . . . . . . . . . . 22 6.9 memory card interface (mci) . . . . . . . . . . . . . 23 6.10 universal serial bus 2.0 high speed on-the-go (otg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.11 dma controller . . . . . . . . . . . . . . . . . . . . . . . . 24 6.12 interrupt controller . . . . . . . . . . . . . . . . . . . . . 25 6.13 multi-layer ahb. . . . . . . . . . . . . . . . . . . . . . . . 25 6.14 apb bridge . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.15 clock generation unit (cgu) . . . . . . . . . . . . . 27 6.16 watchdog timer (wdt) . . . . . . . . . . . . . . . . . 29 6.17 input/output configuration module (ioconfig) . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.18 10-bit analog-to-digital converter (adc10b) . 30 6.19 event router . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.20 random number generator (rng) . . . . . . . . 32 6.21 aes decryption (lpc3154 only) . . . . . . . . . . . 32 6.22 secure one-time programmable (otp) memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.23 serial peripheral interfac e (spi) . . . . . . . . . . . 32 6.24 universal asynchronous receiver transmitter (uart) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.25 pulse code modulation (pcm) interface . . . . 33 6.26 lcd interface . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.27 i 2 c-bus master/slave interface . . . . . . . . . . . . 34 6.28 lcd/nand flash/sdram mu ltiplexing . . . . . 35 6.28.1 pin connections . . . . . . . . . . . . . . . . . . . . . . . 35 6.28.2 multiplexing between lcd and mpmc . . . . . . 37 6.28.3 supply domains . . . . . . . . . . . . . . . . . . . . . . . 38 6.29 timer module . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.30 pulse width modulation (pwm) module . . . . . 39 6.31 system control registers . . . . . . . . . . . . . . . . 39 6.32 audio subsystem (adss) . . . . . . . . . . . . . . . 39 6.32.1 i 2 s0/1 digital audio input/output . . . . . . . . . . . 40 7 functional description of the analog die blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.1 analog die . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.2 audio codec . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.2.1 stereo digital-to-analog converter (sdac) . . 42 7.2.2 class ab headphone amplifier. . . . . . . . . . . . 43 7.2.3 stereo analog-to-digital converter (sadc) for audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.3 li-ion charger . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.4 usb charge pump (host mode) . . . . . . . . . . . 45 7.5 power supply unit (psu). . . . . . . . . . . . . . . . 45 7.6 real-time clock (rtc) . . . . . . . . . . . . . . . . . 47 8 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 48 9 static characteristics . . . . . . . . . . . . . . . . . . . 48 9.1 digital die . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.2 analog die . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.2.1 psu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.2.1.1 psu_vout1 efficiency . . . . . . . . . . . . . . . . . 56 9.2.1.2 psu_vout2 efficiency . . . . . . . . . . . . . . . . . 57 9.2.2 li-ion charger . . . . . . . . . . . . . . . . . . . . . . . . . 59 10 dynamic characteristics. . . . . . . . . . . . . . . . . 60 10.1 digital die . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 10.1.1 lcd controller . . . . . . . . . . . . . . . . . . . . . . . . 60 10.1.1.1 intel 8080 mode . . . . . . . . . . . . . . . . . . . . . . . 60 10.1.1.2 motorola 6800 mode . . . . . . . . . . . . . . . . . . . 61 10.1.1.3 serial mode . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10.1.2 sram controller. . . . . . . . . . . . . . . . . . . . . . . 63 10.1.3 sdram controller . . . . . . . . . . . . . . . . . . . . . 65 10.2 nand flash memory contro ller . . . . . . . . . . . 69 10.2.1 crystal oscillator. . . . . . . . . . . . . . . . . . . . . . . 70 10.2.2 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10.2.2.1 texas instruments synchronous serial mode (ssp mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 10.2.3 i 2 s-interface . . . . . . . . . . . . . . . . . . . . . . . . . . 74 10.2.4 i 2 c-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 10.2.5 usb interface. . . . . . . . . . . . . . . . . . . . . . . . . 77 10.2.6 10-bit adc . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 10.3 analog die/audio system . . . . . . . . . . . . . . . . 78 11 application information . . . . . . . . . . . . . . . . . 79 12 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 13 package outline. . . . . . . . . . . . . . . . . . . . . . . . 81 14 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 82 15 revision history . . . . . . . . . . . . . . . . . . . . . . . 84
dr aft dr aft draft dr d raft draft dra f t draf d raft draft draft draft draft d draft d raft dra f t draft draft draft dra nxp semiconductors lpc3152/3154 ? nxp b.v. 2010. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 27 may 2010 document identifier: lpc3152_3154 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 16 legal information. . . . . . . . . . . . . . . . . . . . . . . 85 16.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 85 16.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 16.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 16.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 86 17 contact information. . . . . . . . . . . . . . . . . . . . . 86 18 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

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